2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/errno.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/ccm_regs.h>
28 #include <asm/arch/clock.h>
31 PLL_SYS, /* System PLL */
32 PLL_BUS, /* System Bus PLL*/
33 PLL_USBOTG, /* OTG USB PLL */
34 PLL_ENET, /* ENET PLL */
37 struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
39 void enable_usboh3_clk(unsigned char enable)
43 reg = __raw_readl(&imx_ccm->CCGR6);
45 reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
47 reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
48 __raw_writel(reg, &imx_ccm->CCGR6);
52 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
58 div = __raw_readl(&imx_ccm->analog_pll_sys);
59 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
61 return infreq * (div >> 1);
63 div = __raw_readl(&imx_ccm->analog_pll_528);
64 div &= BM_ANADIG_PLL_528_DIV_SELECT;
66 return infreq * (20 + (div << 1));
68 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
69 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
71 return infreq * (20 + (div << 1));
73 div = __raw_readl(&imx_ccm->analog_pll_enet);
74 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
76 return (div == 3 ? 125000000 : 25000000 * (div << 1));
83 static u32 get_mcu_main_clk(void)
87 reg = __raw_readl(&imx_ccm->cacrr);
88 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
89 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
90 freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
92 return freq / (reg + 1);
95 static u32 get_periph_clk(void)
99 reg = __raw_readl(&imx_ccm->cbcdr);
100 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
101 reg = __raw_readl(&imx_ccm->cbcmr);
102 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
103 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
107 freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
111 freq = CONFIG_SYS_MX6_HCLK;
117 reg = __raw_readl(&imx_ccm->cbcmr);
118 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
119 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
123 freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
126 freq = PLL2_PFD2_FREQ;
129 freq = PLL2_PFD0_FREQ;
132 freq = PLL2_PFD2_DIV_FREQ;
143 static u32 get_ahb_clk(void)
147 reg = __raw_readl(&imx_ccm->cbcdr);
148 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
149 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
151 return get_periph_clk() / (ahb_podf + 1);
154 static u32 get_ipg_clk(void)
158 reg = __raw_readl(&imx_ccm->cbcdr);
159 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
160 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
162 return get_ahb_clk() / (ipg_podf + 1);
165 static u32 get_ipg_per_clk(void)
167 u32 reg, perclk_podf;
169 reg = __raw_readl(&imx_ccm->cscmr1);
170 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
172 return get_ipg_clk() / (perclk_podf + 1);
175 static u32 get_uart_clk(void)
179 reg = __raw_readl(&imx_ccm->cscdr1);
180 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
181 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
183 return PLL3_80M / (uart_podf + 1);
186 static u32 get_cspi_clk(void)
190 reg = __raw_readl(&imx_ccm->cscdr2);
191 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
192 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
194 return PLL3_60M / (cspi_podf + 1);
197 static u32 get_axi_clk(void)
199 u32 root_freq, axi_podf;
200 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
202 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
203 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
205 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
206 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
207 root_freq = PLL2_PFD2_FREQ;
209 root_freq = PLL3_PFD1_FREQ;
211 root_freq = get_periph_clk();
213 return root_freq / (axi_podf + 1);
216 static u32 get_emi_slow_clk(void)
218 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
220 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
221 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
222 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
223 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
224 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
226 switch (emi_clk_sel) {
228 root_freq = get_axi_clk();
231 root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
234 root_freq = PLL2_PFD2_FREQ;
237 root_freq = PLL2_PFD0_FREQ;
241 return root_freq / (emi_slow_pof + 1);
244 static u32 get_mmdc_ch0_clk(void)
246 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
247 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
248 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
250 return get_periph_clk() / (mmdc_ch0_podf + 1);
253 static u32 get_usdhc_clk(u32 port)
255 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
256 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
257 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
261 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
262 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
263 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
267 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
268 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
269 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
273 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
274 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
275 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
279 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
280 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
281 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
289 root_freq = PLL2_PFD0_FREQ;
291 root_freq = PLL2_PFD2_FREQ;
293 return root_freq / (usdhc_podf + 1);
296 u32 imx_get_uartclk(void)
298 return get_uart_clk();
301 u32 imx_get_fecclk(void)
303 return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
306 unsigned int mxc_get_clock(enum mxc_clock clk)
310 return get_mcu_main_clk();
312 return get_periph_clk();
314 return get_ahb_clk();
316 return get_ipg_clk();
318 return get_ipg_per_clk();
320 return get_uart_clk();
322 return get_cspi_clk();
324 return get_axi_clk();
325 case MXC_EMI_SLOW_CLK:
326 return get_emi_slow_clk();
328 return get_mmdc_ch0_clk();
330 return get_usdhc_clk(0);
332 return get_usdhc_clk(1);
334 return get_usdhc_clk(2);
336 return get_usdhc_clk(3);
338 return get_ahb_clk();
347 * Dump some core clockes.
349 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
352 freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
353 printf("PLL_SYS %8d MHz\n", freq / 1000000);
354 freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
355 printf("PLL_BUS %8d MHz\n", freq / 1000000);
356 freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
357 printf("PLL_OTG %8d MHz\n", freq / 1000000);
358 freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
359 printf("PLL_NET %8d MHz\n", freq / 1000000);
362 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
363 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
364 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
365 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
366 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
367 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
368 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
369 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
370 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
371 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
372 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
373 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
378 /***************************************************/
381 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,