3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/pl310.h>
13 #include <asm/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/boot_mode.h>
19 #include <asm/imx-common/dma.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
40 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
41 u32 reg = readl(&anatop->digprog_sololite);
42 u32 type = ((reg >> 16) & 0xff);
44 if (type != MXC_CPU_MX6SL) {
45 reg = readl(&anatop->digprog);
46 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
47 u32 cfg = readl(&scu->config) & 3;
48 type = ((reg >> 16) & 0xff);
49 if (type == MXC_CPU_MX6DL) {
51 type = MXC_CPU_MX6SOLO;
54 if (type == MXC_CPU_MX6Q) {
60 reg &= 0xff; /* mx6 silicon revision */
61 return (type << 12) | (reg + 0x10);
64 #ifdef CONFIG_REVISION_TAG
65 u32 __weak get_board_rev(void)
67 u32 cpurev = get_cpu_rev();
68 u32 type = ((cpurev >> 12) & 0xff);
69 if (type == MXC_CPU_MX6SOLO)
70 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
72 if (type == MXC_CPU_MX6D)
73 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
81 struct aipstz_regs *aips1, *aips2;
83 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
84 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
87 * Set all MPROTx to be non-bufferable, trusted for R/W,
88 * not forced to user-mode.
90 writel(0x77777777, &aips1->mprot0);
91 writel(0x77777777, &aips1->mprot1);
92 writel(0x77777777, &aips2->mprot0);
93 writel(0x77777777, &aips2->mprot1);
96 * Set all OPACRx to be non-bufferable, not require
97 * supervisor privilege level for access,allow for
98 * write access and untrusted master access.
100 writel(0x00000000, &aips1->opacr0);
101 writel(0x00000000, &aips1->opacr1);
102 writel(0x00000000, &aips1->opacr2);
103 writel(0x00000000, &aips1->opacr3);
104 writel(0x00000000, &aips1->opacr4);
105 writel(0x00000000, &aips2->opacr0);
106 writel(0x00000000, &aips2->opacr1);
107 writel(0x00000000, &aips2->opacr2);
108 writel(0x00000000, &aips2->opacr3);
109 writel(0x00000000, &aips2->opacr4);
112 static void clear_ldo_ramp(void)
114 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
117 /* ROM may modify LDO ramp up time according to fuse setting, so in
118 * order to be in the safe side we neeed to reset these settings to
119 * match the reset value: 0'b00
121 reg = readl(&anatop->ana_misc2);
122 reg &= ~(0x3f << 24);
123 writel(reg, &anatop->ana_misc2);
129 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
130 * them to the specified millivolt level.
131 * Possible values are from 0.725V to 1.450V in steps of
134 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
136 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
137 u32 val, step, old, reg = readl(&anatop->reg_core);
141 val = 0x00; /* Power gated off */
143 val = 0x1F; /* Power FET switched full on. No regulation */
145 val = (mv - 700) / 25;
163 old = (reg & (0x1F << shift)) >> shift;
164 step = abs(val - old);
168 reg = (reg & ~(0x1F << shift)) | (val << shift);
169 writel(reg, &anatop->reg_core);
172 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
180 static void imx_set_wdog_powerdown(bool enable)
182 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
183 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
185 /* Write to the PDE (Power Down Enable) bit */
186 writew(enable, &wdog1->wmcr);
187 writew(enable, &wdog2->wmcr);
190 static void set_ahb_rate(u32 val)
192 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
195 div = get_periph_clk() / val - 1;
196 reg = readl(&mxc_ccm->cbcdr);
198 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
199 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
202 static void clear_mmdc_ch_mask(void)
204 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
206 /* Clear MMDC channel mask */
207 writel(0, &mxc_ccm->ccdr);
210 int arch_cpu_init(void)
214 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
215 clear_mmdc_ch_mask();
218 * When low freq boot is enabled, ROM will not set AHB
219 * freq, so we need to ensure AHB freq is 132MHz in such
222 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
223 set_ahb_rate(132000000);
225 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
227 #ifdef CONFIG_APBH_DMA
235 int board_postclk_init(void)
237 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
242 #ifndef CONFIG_SYS_DCACHE_OFF
243 void enable_caches(void)
245 /* Avoid random hang when download by usb */
246 invalidate_dcache_all();
247 /* Enable D-cache. I-cache is already enabled in start.S */
252 #if defined(CONFIG_FEC_MXC)
253 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
255 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
256 struct fuse_bank *bank = &ocotp->bank[4];
257 struct fuse_bank4_regs *fuse =
258 (struct fuse_bank4_regs *)bank->fuse_regs;
260 u32 value = readl(&fuse->mac_addr_high);
261 mac[0] = (value >> 8);
264 value = readl(&fuse->mac_addr_low);
265 mac[2] = value >> 24 ;
266 mac[3] = value >> 16 ;
267 mac[4] = value >> 8 ;
273 void boot_mode_apply(unsigned cfg_val)
276 struct src *psrc = (struct src *)SRC_BASE_ADDR;
277 writel(cfg_val, &psrc->gpr9);
278 reg = readl(&psrc->gpr10);
283 writel(reg, &psrc->gpr10);
286 * cfg_val will be used for
287 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
288 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
289 * to SBMR1, which will determine the boot device.
291 const struct boot_mode soc_boot_modes[] = {
292 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
293 /* reserved value should start rom usb */
294 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
295 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
296 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
297 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
298 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
299 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
300 /* 4 bit bus width */
301 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
302 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
303 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
304 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
310 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
311 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
315 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
316 * to make sure PFD is working right, otherwise, PFDs may
317 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
318 * workaround in ROM code, as bus clock need it
321 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
322 ANATOP_PFD_CLKGATE_MASK(1) |
323 ANATOP_PFD_CLKGATE_MASK(2) |
324 ANATOP_PFD_CLKGATE_MASK(3);
325 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
326 ANATOP_PFD_CLKGATE_MASK(1) |
327 ANATOP_PFD_CLKGATE_MASK(3);
330 * Don't reset PFD2 on DL/S
333 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
334 writel(mask480, &anatop->pfd_480_set);
335 writel(mask528, &anatop->pfd_528_set);
336 writel(mask480, &anatop->pfd_480_clr);
337 writel(mask528, &anatop->pfd_528_clr);
340 #ifdef CONFIG_IMX_HDMI
341 void imx_enable_hdmi_phy(void)
343 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
345 reg = readb(&hdmi->phy_conf0);
346 reg |= HDMI_PHY_CONF0_PDZ_MASK;
347 writeb(reg, &hdmi->phy_conf0);
349 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
350 writeb(reg, &hdmi->phy_conf0);
352 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
353 writeb(reg, &hdmi->phy_conf0);
354 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
357 void imx_setup_hdmi(void)
359 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
360 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
363 /* Turn on HDMI PHY clock */
364 reg = readl(&mxc_ccm->CCGR2);
365 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
366 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
367 writel(reg, &mxc_ccm->CCGR2);
368 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
369 reg = readl(&mxc_ccm->chsccdr);
370 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
371 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
372 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
373 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
374 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
375 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
376 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
377 writel(reg, &mxc_ccm->chsccdr);
381 #ifndef CONFIG_SYS_L2CACHE_OFF
382 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
383 void v7_outer_cache_enable(void)
385 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
388 #if defined CONFIG_MX6SL
389 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
390 val = readl(&iomux->gpr[11]);
391 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
392 /* L2 cache configured as OCRAM, reset it */
393 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
394 writel(val, &iomux->gpr[11]);
398 writel(0x132, &pl310->pl310_tag_latency_ctrl);
399 writel(0x132, &pl310->pl310_data_latency_ctrl);
401 val = readl(&pl310->pl310_prefetch_ctrl);
403 /* Turn on the L2 I/D prefetch */
407 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
408 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
409 * But according to ARM PL310 errata: 752271
410 * ID: 752271: Double linefill feature can cause data corruption
411 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
412 * Workaround: The only workaround to this erratum is to disable the
413 * double linefill feature. This is the default behavior.
419 writel(val, &pl310->pl310_prefetch_ctrl);
421 val = readl(&pl310->pl310_power_ctrl);
422 val |= L2X0_DYNAMIC_CLK_GATING_EN;
423 val |= L2X0_STNDBY_MODE_EN;
424 writel(val, &pl310->pl310_power_ctrl);
426 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
429 void v7_outer_cache_disable(void)
431 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
433 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
435 #endif /* !CONFIG_SYS_L2CACHE_OFF */