3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/imx-common/boot_mode.h>
45 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
46 u32 reg = readl(&anatop->digprog_sololite);
47 u32 type = ((reg >> 16) & 0xff);
49 if (type != MXC_CPU_MX6SL) {
50 reg = readl(&anatop->digprog);
51 type = ((reg >> 16) & 0xff);
52 if (type == MXC_CPU_MX6DL) {
53 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
54 u32 cfg = readl(&scu->config) & 3;
57 type = MXC_CPU_MX6SOLO;
60 reg &= 0xff; /* mx6 silicon revision */
61 return (type << 12) | (reg + 0x10);
64 #ifdef CONFIG_REVISION_TAG
65 u32 __weak get_board_rev(void)
67 u32 cpurev = get_cpu_rev();
68 u32 type = ((cpurev >> 12) & 0xff);
69 if (type == MXC_CPU_MX6SOLO)
70 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
78 struct aipstz_regs *aips1, *aips2;
80 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
81 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
84 * Set all MPROTx to be non-bufferable, trusted for R/W,
85 * not forced to user-mode.
87 writel(0x77777777, &aips1->mprot0);
88 writel(0x77777777, &aips1->mprot1);
89 writel(0x77777777, &aips2->mprot0);
90 writel(0x77777777, &aips2->mprot1);
93 * Set all OPACRx to be non-bufferable, not require
94 * supervisor privilege level for access,allow for
95 * write access and untrusted master access.
97 writel(0x00000000, &aips1->opacr0);
98 writel(0x00000000, &aips1->opacr1);
99 writel(0x00000000, &aips1->opacr2);
100 writel(0x00000000, &aips1->opacr3);
101 writel(0x00000000, &aips1->opacr4);
102 writel(0x00000000, &aips2->opacr0);
103 writel(0x00000000, &aips2->opacr1);
104 writel(0x00000000, &aips2->opacr2);
105 writel(0x00000000, &aips2->opacr3);
106 writel(0x00000000, &aips2->opacr4);
112 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
113 * them to the specified millivolt level.
114 * Possible values are from 0.725V to 1.450V in steps of
117 void set_vddsoc(u32 mv)
119 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
120 u32 val, reg = readl(&anatop->reg_core);
123 val = 0x00; /* Power gated off */
125 val = 0x1F; /* Power FET switched full on. No regulation */
127 val = (mv - 700) / 25;
130 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
131 * and set them to the calculated value (0.7V + val * 0.25V)
133 reg = (reg & ~(0x1F << 18)) | (val << 18);
134 writel(reg, &anatop->reg_core);
137 static void imx_set_wdog_powerdown(bool enable)
139 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
140 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
142 /* Write to the PDE (Power Down Enable) bit */
143 writew(enable, &wdog1->wmcr);
144 writew(enable, &wdog2->wmcr);
147 int arch_cpu_init(void)
151 set_vddsoc(1200); /* Set VDDSOC to 1.2V */
153 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
157 #ifndef CONFIG_SYS_DCACHE_OFF
158 void enable_caches(void)
160 /* Enable D-cache. I-cache is already enabled in start.S */
165 #if defined(CONFIG_FEC_MXC)
166 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
168 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
169 struct fuse_bank *bank = &iim->bank[4];
170 struct fuse_bank4_regs *fuse =
171 (struct fuse_bank4_regs *)bank->fuse_regs;
173 u32 value = readl(&fuse->mac_addr_high);
174 mac[0] = (value >> 8);
177 value = readl(&fuse->mac_addr_low);
178 mac[2] = value >> 24 ;
179 mac[3] = value >> 16 ;
180 mac[4] = value >> 8 ;
186 void boot_mode_apply(unsigned cfg_val)
189 struct src *psrc = (struct src *)SRC_BASE_ADDR;
190 writel(cfg_val, &psrc->gpr9);
191 reg = readl(&psrc->gpr10);
196 writel(reg, &psrc->gpr10);
199 * cfg_val will be used for
200 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
201 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
202 * to SBMR1, which will determine the boot device.
204 const struct boot_mode soc_boot_modes[] = {
205 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
206 /* reserved value should start rom usb */
207 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
208 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
209 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
210 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
211 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
212 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
213 /* 4 bit bus width */
214 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
215 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
216 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
217 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},