3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
18 #include <asm/imx-common/hab.h>
20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h>
23 #include <imx_thermal.h>
39 #if defined(CONFIG_IMX_THERMAL)
40 static const struct imx_thermal_plat imx6_thermal_plat = {
41 .regs = (void *)ANATOP_BASE_ADDR,
46 U_BOOT_DEVICE(imx6_thermal) = {
47 .name = "imx_thermal",
48 .platdata = &imx6_thermal_plat,
52 #if defined(CONFIG_SECURE_BOOT)
53 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
61 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
62 return readl(&scu->config) & 3;
67 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
68 u32 reg = readl(&anatop->digprog_sololite);
69 u32 type = ((reg >> 16) & 0xff);
72 if (type != MXC_CPU_MX6SL) {
73 reg = readl(&anatop->digprog);
74 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
75 cfg = readl(&scu->config) & 3;
76 type = ((reg >> 16) & 0xff);
77 if (type == MXC_CPU_MX6DL) {
79 type = MXC_CPU_MX6SOLO;
82 if (type == MXC_CPU_MX6Q) {
88 major = ((reg >> 8) & 0xff);
90 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
96 reg &= 0xff; /* mx6 silicon revision */
97 return (type << 12) | (reg + (0x10 * (major + 1)));
101 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
102 * defines a 2-bit SPEED_GRADING
104 #define OCOTP_CFG3_SPEED_SHIFT 16
105 #define OCOTP_CFG3_SPEED_800MHZ 0
106 #define OCOTP_CFG3_SPEED_850MHZ 1
107 #define OCOTP_CFG3_SPEED_1GHZ 2
108 #define OCOTP_CFG3_SPEED_1P2GHZ 3
110 u32 get_cpu_speed_grade_hz(void)
112 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
113 struct fuse_bank *bank = &ocotp->bank[0];
114 struct fuse_bank0_regs *fuse =
115 (struct fuse_bank0_regs *)bank->fuse_regs;
118 val = readl(&fuse->cfg3);
119 val >>= OCOTP_CFG3_SPEED_SHIFT;
123 /* Valid for IMX6DQ */
124 case OCOTP_CFG3_SPEED_1P2GHZ:
125 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
127 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
128 case OCOTP_CFG3_SPEED_1GHZ:
130 /* Valid for IMX6DQ */
131 case OCOTP_CFG3_SPEED_850MHZ:
132 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
134 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
135 case OCOTP_CFG3_SPEED_800MHZ:
142 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
143 * defines a 2-bit Temperature Grade
145 * return temperature grade and min/max temperature in celcius
147 #define OCOTP_MEM0_TEMP_SHIFT 6
149 u32 get_cpu_temp_grade(int *minc, int *maxc)
151 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
152 struct fuse_bank *bank = &ocotp->bank[1];
153 struct fuse_bank1_regs *fuse =
154 (struct fuse_bank1_regs *)bank->fuse_regs;
157 val = readl(&fuse->mem0);
158 val >>= OCOTP_MEM0_TEMP_SHIFT;
162 if (val == TEMP_AUTOMOTIVE) {
165 } else if (val == TEMP_INDUSTRIAL) {
168 } else if (val == TEMP_EXTCOMMERCIAL) {
179 #ifdef CONFIG_REVISION_TAG
180 u32 __weak get_board_rev(void)
182 u32 cpurev = get_cpu_rev();
183 u32 type = ((cpurev >> 12) & 0xff);
184 if (type == MXC_CPU_MX6SOLO)
185 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
187 if (type == MXC_CPU_MX6D)
188 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
194 static void clear_ldo_ramp(void)
196 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
199 /* ROM may modify LDO ramp up time according to fuse setting, so in
200 * order to be in the safe side we neeed to reset these settings to
201 * match the reset value: 0'b00
203 reg = readl(&anatop->ana_misc2);
204 reg &= ~(0x3f << 24);
205 writel(reg, &anatop->ana_misc2);
209 * Set the PMU_REG_CORE register
211 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
212 * Possible values are from 0.725V to 1.450V in steps of
215 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
217 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
218 u32 val, step, old, reg = readl(&anatop->reg_core);
222 val = 0x00; /* Power gated off */
224 val = 0x1F; /* Power FET switched full on. No regulation */
226 val = (mv - 700) / 25;
244 old = (reg & (0x1F << shift)) >> shift;
245 step = abs(val - old);
249 reg = (reg & ~(0x1F << shift)) | (val << shift);
250 writel(reg, &anatop->reg_core);
253 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
261 static void set_ahb_rate(u32 val)
263 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
266 div = get_periph_clk() / val - 1;
267 reg = readl(&mxc_ccm->cbcdr);
269 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
270 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
273 static void clear_mmdc_ch_mask(void)
275 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
277 reg = readl(&mxc_ccm->ccdr);
279 /* Clear MMDC channel mask */
280 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
281 writel(reg, &mxc_ccm->ccdr);
284 static void init_bandgap(void)
286 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
288 * Ensure the bandgap has stabilized.
290 while (!(readl(&anatop->ana_misc0) & 0x80))
293 * For best noise performance of the analog blocks using the
294 * outputs of the bandgap, the reftop_selfbiasoff bit should
297 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
302 static void set_preclk_from_osc(void)
304 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
307 reg = readl(&mxc_ccm->cscmr1);
308 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
309 writel(reg, &mxc_ccm->cscmr1);
313 int arch_cpu_init(void)
317 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
318 clear_mmdc_ch_mask();
321 * Disable self-bias circuit in the analog bandap.
322 * The self-bias circuit is used by the bandgap during startup.
323 * This bit should be set after the bandgap has initialized.
328 * When low freq boot is enabled, ROM will not set AHB
329 * freq, so we need to ensure AHB freq is 132MHz in such
332 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
333 set_ahb_rate(132000000);
335 /* Set perclk to source from OSC 24MHz */
336 #if defined(CONFIG_MX6SL)
337 set_preclk_from_osc();
340 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
342 #ifdef CONFIG_APBH_DMA
352 int board_postclk_init(void)
354 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
359 #if defined(CONFIG_FEC_MXC)
360 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
362 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
363 struct fuse_bank *bank = &ocotp->bank[4];
364 struct fuse_bank4_regs *fuse =
365 (struct fuse_bank4_regs *)bank->fuse_regs;
367 u32 value = readl(&fuse->mac_addr_high);
368 mac[0] = (value >> 8);
371 value = readl(&fuse->mac_addr_low);
372 mac[2] = value >> 24 ;
373 mac[3] = value >> 16 ;
374 mac[4] = value >> 8 ;
381 * cfg_val will be used for
382 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
383 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
384 * instead of SBMR1 to determine the boot device.
386 const struct boot_mode soc_boot_modes[] = {
387 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
388 /* reserved value should start rom usb */
389 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
390 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
391 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
392 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
393 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
394 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
395 /* 4 bit bus width */
396 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
397 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
398 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
399 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
405 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
406 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
409 u32 reg, periph1, periph2;
411 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
414 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
415 * to make sure PFD is working right, otherwise, PFDs may
416 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
417 * workaround in ROM code, as bus clock need it
420 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
421 ANATOP_PFD_CLKGATE_MASK(1) |
422 ANATOP_PFD_CLKGATE_MASK(2) |
423 ANATOP_PFD_CLKGATE_MASK(3);
424 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
425 ANATOP_PFD_CLKGATE_MASK(3);
427 reg = readl(&ccm->cbcmr);
428 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
429 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
430 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
431 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
433 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
434 if ((periph2 != 0x2) && (periph1 != 0x2))
435 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
437 if ((periph2 != 0x1) && (periph1 != 0x1) &&
438 (periph2 != 0x3) && (periph1 != 0x3))
439 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
441 writel(mask480, &anatop->pfd_480_set);
442 writel(mask528, &anatop->pfd_528_set);
443 writel(mask480, &anatop->pfd_480_clr);
444 writel(mask528, &anatop->pfd_528_clr);
447 #ifdef CONFIG_IMX_HDMI
448 void imx_enable_hdmi_phy(void)
450 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
452 reg = readb(&hdmi->phy_conf0);
453 reg |= HDMI_PHY_CONF0_PDZ_MASK;
454 writeb(reg, &hdmi->phy_conf0);
456 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
457 writeb(reg, &hdmi->phy_conf0);
459 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
460 writeb(reg, &hdmi->phy_conf0);
461 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
464 void imx_setup_hdmi(void)
466 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
467 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
470 /* Turn on HDMI PHY clock */
471 reg = readl(&mxc_ccm->CCGR2);
472 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
473 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
474 writel(reg, &mxc_ccm->CCGR2);
475 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
476 reg = readl(&mxc_ccm->chsccdr);
477 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
478 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
479 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
480 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
481 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
482 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
483 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
484 writel(reg, &mxc_ccm->chsccdr);