2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
5 * Peng Fan <Peng.Fan@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
19 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
21 static struct clk_root_map root_array[] = {
22 {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
23 {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
24 PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
25 PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
27 {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
28 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
29 PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
30 PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
32 {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
33 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
34 PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
35 PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
37 {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
38 {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
39 PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
40 PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
42 {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
43 {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
44 PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
45 PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
47 {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
48 {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
49 PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
50 PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
52 {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
53 {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
54 PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
55 PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
57 {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
58 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
59 PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
60 PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
62 {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
63 {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
65 {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
66 {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
68 {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
69 {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
70 PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
71 PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
73 {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
74 {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
75 PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
76 PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
78 {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
79 {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
80 PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
81 PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
83 {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
84 {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
85 PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
86 PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
88 {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
89 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
90 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
91 EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
93 {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
94 {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
95 PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
96 PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
98 {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
99 {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
100 EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
101 PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
103 {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
104 {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
105 PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
106 PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
108 {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
109 {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
110 PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
111 PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
113 {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
114 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
115 PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
116 PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
118 {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
119 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
120 PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
121 PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
123 {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
124 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
125 PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
126 PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
128 {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
129 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
130 PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
131 PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
133 {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
134 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
135 PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
136 PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
138 {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
139 {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
140 PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
141 PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
143 {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
144 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
145 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
146 EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
148 {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
149 {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
150 PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
151 PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
153 {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
154 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
155 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
156 EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
158 {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
159 {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
160 PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
161 PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
163 {EIM_CLK_ROOT, CCM_IP_CHANNEL,
164 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
165 PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
166 PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
168 {NAND_CLK_ROOT, CCM_IP_CHANNEL,
169 {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
170 PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
171 PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
173 {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
174 {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
175 PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
176 PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
178 {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
179 {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
180 PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
181 PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
183 {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
184 {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
185 PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
186 PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
188 {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
189 {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
190 PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
191 PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
193 {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
194 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
195 PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
196 EXT_CLK_1, EXT_CLK_4}
198 {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
199 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
200 PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
201 EXT_CLK_1, EXT_CLK_3}
203 {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
204 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
205 PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
206 PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
208 {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
209 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
210 PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
211 PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
213 {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
214 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
215 PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
216 PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
218 {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
219 {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
220 PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
221 PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
223 {UART1_CLK_ROOT, CCM_IP_CHANNEL,
224 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
225 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
226 EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
228 {UART2_CLK_ROOT, CCM_IP_CHANNEL,
229 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
230 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
231 EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
233 {UART3_CLK_ROOT, CCM_IP_CHANNEL,
234 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
235 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
236 EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
238 {UART4_CLK_ROOT, CCM_IP_CHANNEL,
239 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
240 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
241 EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
243 {UART5_CLK_ROOT, CCM_IP_CHANNEL,
244 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
245 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
246 EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
248 {UART6_CLK_ROOT, CCM_IP_CHANNEL,
249 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
250 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
251 EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
253 {UART7_CLK_ROOT, CCM_IP_CHANNEL,
254 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
255 PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
256 EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
258 {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
259 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
260 PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
261 PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
263 {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
264 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
265 PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
266 PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
268 {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
269 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
270 PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
271 PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
273 {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
274 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
275 PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
276 PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
278 {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
279 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
280 PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
281 REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
283 {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
284 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
285 PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
286 REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
288 {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
289 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
290 PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
291 REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
293 {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
294 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
295 PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
296 REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
298 {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
299 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
300 PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
301 REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
303 {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
304 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
305 PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
306 REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
308 {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
309 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
310 PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
311 PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
313 {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
314 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
315 PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
316 PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
318 {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
319 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
320 PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
321 PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
323 {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
324 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
325 PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
326 PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
328 {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
329 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
330 PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
331 PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
333 {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
334 {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
335 PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
336 PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
338 {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
339 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
340 PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
341 EXT_CLK_1, EXT_CLK_3}
343 {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
344 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
345 PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
346 REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
348 {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
349 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
350 PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
351 PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
353 {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
354 {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
355 PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
356 PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
358 {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
359 {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
360 PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
361 PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
363 {IPP_DO_CLKO1, CCM_IP_CHANNEL,
364 {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
365 PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
366 PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
368 {IPP_DO_CLKO2, CCM_IP_CHANNEL,
369 {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
370 PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
371 PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
375 /* select which entry of root_array */
376 static int select(enum clk_root_index clock_id)
379 struct clk_root_map *p = root_array;
381 size = ARRAY_SIZE(root_array);
383 for (i = 0; i < size; i++, p++) {
384 if (clock_id == p->entry)
391 static int src_supported(int entry, enum clk_root_src clock_src)
394 struct clk_root_map *p = &root_array[entry];
396 if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
401 for (i = 0; i < size; i++) {
402 if (p->src_mux[i] == clock_src)
409 /* Set src for clock root slice. */
410 int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
412 int root_entry, src_entry;
415 if (clock_id >= CLK_ROOT_MAX)
418 root_entry = select(clock_id);
422 src_entry = src_supported(root_entry, clock_src);
426 reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
427 reg &= ~CLK_ROOT_MUX_MASK;
428 reg |= src_entry << CLK_ROOT_MUX_SHIFT;
429 __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
434 /* Get src of a clock root slice. */
435 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
439 struct clk_root_map *p;
441 if (clock_id >= CLK_ROOT_MAX)
444 val = __raw_readl(&imx_ccm->root[clock_id].target_root);
445 val &= CLK_ROOT_MUX_MASK;
446 val >>= CLK_ROOT_MUX_SHIFT;
448 root_entry = select(clock_id);
452 p = &root_array[root_entry];
453 *p_clock_src = p->src_mux[val];
458 int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
461 struct clk_root_map *p;
464 if (clock_id >= CLK_ROOT_MAX)
467 root_entry = select(clock_id);
471 p = &root_array[root_entry];
473 if ((p->type == CCM_CORE_CHANNEL) ||
474 (p->type == CCM_DRAM_PHYM_CHANNEL) ||
475 (p->type == CCM_DRAM_CHANNEL)) {
476 if (pre_div != CLK_ROOT_PRE_DIV1) {
477 printf("Error pre div!\n");
482 reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
483 reg &= ~CLK_ROOT_PRE_DIV_MASK;
484 reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
485 __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
490 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
494 struct clk_root_map *p;
496 if (clock_id >= CLK_ROOT_MAX)
499 root_entry = select(clock_id);
503 p = &root_array[root_entry];
505 if ((p->type == CCM_CORE_CHANNEL) ||
506 (p->type == CCM_DRAM_PHYM_CHANNEL) ||
507 (p->type == CCM_DRAM_CHANNEL)) {
512 val = __raw_readl(&imx_ccm->root[clock_id].target_root);
513 val &= CLK_ROOT_PRE_DIV_MASK;
514 val >>= CLK_ROOT_PRE_DIV_SHIFT;
521 int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
525 if (clock_id >= CLK_ROOT_MAX)
528 if (clock_id == DRAM_PHYM_CLK_ROOT) {
529 if (div != CLK_ROOT_POST_DIV1) {
530 printf("Error post div!\n");
535 /* Only 3 bit post div. */
536 if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
537 printf("Error post div!\n");
541 reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
542 reg &= ~CLK_ROOT_POST_DIV_MASK;
543 reg |= div << CLK_ROOT_POST_DIV_SHIFT;
544 __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
549 int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
553 if (clock_id >= CLK_ROOT_MAX)
556 if (clock_id == DRAM_PHYM_CLK_ROOT) {
561 val = __raw_readl(&imx_ccm->root[clock_id].target_root);
562 if (clock_id == DRAM_CLK_ROOT)
563 val &= DRAM_CLK_ROOT_POST_DIV_MASK;
565 val &= CLK_ROOT_POST_DIV_MASK;
566 val >>= CLK_ROOT_POST_DIV_SHIFT;
573 int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
578 struct clk_root_map *p;
580 if (clock_id >= CLK_ROOT_MAX)
583 root_entry = select(clock_id);
587 p = &root_array[root_entry];
589 if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
590 printf("Auto postdiv not supported.!\n");
595 * Each time only one filed can be changed, no use target_root_set.
597 val = __raw_readl(&imx_ccm->root[clock_id].target_root);
598 val &= ~CLK_ROOT_AUTO_DIV_MASK;
599 val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
602 val |= CLK_ROOT_AUTO_EN;
604 val &= ~CLK_ROOT_AUTO_EN;
606 __raw_writel(val, &imx_ccm->root[clock_id].target_root);
611 int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
616 struct clk_root_map *p;
618 if (clock_id >= CLK_ROOT_MAX)
621 root_entry = select(clock_id);
625 p = &root_array[root_entry];
628 * Only bus/ahb channel supports auto div.
629 * If unsupported, just set auto_en and div with 0.
631 if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
637 val = __raw_readl(&imx_ccm->root[clock_id].target_root);
638 if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
643 val &= CLK_ROOT_AUTO_DIV_MASK;
644 val >>= CLK_ROOT_AUTO_DIV_SHIFT;
651 int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
653 if (clock_id >= CLK_ROOT_MAX)
656 *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
661 int clock_set_target_val(enum clk_root_index clock_id, u32 val)
663 if (clock_id >= CLK_ROOT_MAX)
666 __raw_writel(val, &imx_ccm->root[clock_id].target_root);
671 /* Auto_div and auto_en is ignored, they are rarely used. */
672 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
673 enum root_post_div post_div, enum clk_root_src clock_src)
676 int root_entry, src_entry;
677 struct clk_root_map *p;
679 if (clock_id >= CLK_ROOT_MAX)
682 root_entry = select(clock_id);
686 p = &root_array[root_entry];
688 if ((p->type == CCM_CORE_CHANNEL) ||
689 (p->type == CCM_DRAM_PHYM_CHANNEL) ||
690 (p->type == CCM_DRAM_CHANNEL)) {
691 if (pre_div != CLK_ROOT_PRE_DIV1) {
692 printf("Error pre div!\n");
697 /* Only 3 bit post div. */
698 if (p->type == CCM_DRAM_CHANNEL) {
699 if (post_div > CLK_ROOT_POST_DIV7) {
700 printf("Error post div!\n");
705 if (p->type == CCM_DRAM_PHYM_CHANNEL) {
706 if (post_div != CLK_ROOT_POST_DIV1) {
707 printf("Error post div!\n");
712 src_entry = src_supported(root_entry, clock_src);
716 val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
717 post_div << CLK_ROOT_POST_DIV_SHIFT |
718 src_entry << CLK_ROOT_MUX_SHIFT;
720 __raw_writel(val, &imx_ccm->root[clock_id].target_root);
725 int clock_root_enabled(enum clk_root_index clock_id)
729 if (clock_id >= CLK_ROOT_MAX)
733 * No enable bit for DRAM controller and PHY. Just return enabled.
735 if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
738 val = __raw_readl(&imx_ccm->root[clock_id].target_root);
740 return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
743 /* CCGR gate operation */
744 int clock_enable(enum clk_ccgr_index index, bool enable)
746 if (index >= CCGR_MAX)
750 __raw_writel(CCM_CLK_ON_MSK,
751 &imx_ccm->ccgr_array[index].ccgr_set);
753 __raw_writel(CCM_CLK_ON_MSK,
754 &imx_ccm->ccgr_array[index].ccgr_clr);