2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/boot_mode.h>
13 #include <asm/imx-common/dma.h>
14 #include <asm/imx-common/hab.h>
15 #include <asm/imx-common/rdc-sema.h>
16 #include <asm/arch/imx-rdc.h>
17 #include <asm/arch/crm_regs.h>
19 #include <imx_thermal.h>
21 #if defined(CONFIG_IMX_THERMAL)
22 static const struct imx_thermal_plat imx7_thermal_plat = {
23 .regs = (void *)ANATOP_BASE_ADDR,
28 U_BOOT_DEVICE(imx7_thermal) = {
29 .name = "imx_thermal",
30 .platdata = &imx7_thermal_plat,
36 * In current design, if any peripheral was assigned to both A7 and M4,
37 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
38 * low power mode. So M4 sleep will cause some peripherals fail to work
39 * at A7 core side. At default, all resources are in domain 0 - 3.
41 * There are 26 peripherals impacted by this IC issue:
44 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
46 * WDOG1/WDOG2/WDOG3/WDOG4
50 * Software Workaround:
51 * Here we setup some resources to domain 0 where M4 codes will move
52 * the M4 out of this domain. Then M4 is not able to access them any longer.
53 * This is a workaround for ic issue. So the peripherals are not shared
54 * by them. This way requires the uboot implemented the RDC driver and
55 * set the 26 IPs above to domain 0 only. M4 code will assign resource
56 * to its own domain, if it want to use the resource.
58 static rdc_peri_cfg_t const resources[] = {
59 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
60 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
61 (RDC_PER_UART1 | RDC_DOMAIN(0)),
62 (RDC_PER_UART2 | RDC_DOMAIN(0)),
63 (RDC_PER_UART3 | RDC_DOMAIN(0)),
64 (RDC_PER_UART4 | RDC_DOMAIN(0)),
65 (RDC_PER_UART5 | RDC_DOMAIN(0)),
66 (RDC_PER_UART6 | RDC_DOMAIN(0)),
67 (RDC_PER_UART7 | RDC_DOMAIN(0)),
68 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
69 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
70 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
71 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
72 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
73 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
74 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
75 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
76 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
77 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
78 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
79 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
80 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
81 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
82 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
83 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
84 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
87 static void isolate_resource(void)
89 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
93 #if defined(CONFIG_SECURE_BOOT)
94 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
101 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
102 * defines a 2-bit SPEED_GRADING
104 #define OCOTP_TESTER3_SPEED_SHIFT 8
105 #define OCOTP_TESTER3_SPEED_800MHZ 0
106 #define OCOTP_TESTER3_SPEED_850MHZ 1
107 #define OCOTP_TESTER3_SPEED_1GHZ 2
109 u32 get_cpu_speed_grade_hz(void)
111 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
112 struct fuse_bank *bank = &ocotp->bank[1];
113 struct fuse_bank1_regs *fuse =
114 (struct fuse_bank1_regs *)bank->fuse_regs;
117 val = readl(&fuse->tester3);
118 val >>= OCOTP_TESTER3_SPEED_SHIFT;
122 case OCOTP_TESTER3_SPEED_800MHZ:
124 case OCOTP_TESTER3_SPEED_850MHZ:
126 case OCOTP_TESTER3_SPEED_1GHZ:
133 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
134 * defines a 2-bit SPEED_GRADING
136 #define OCOTP_TESTER3_TEMP_SHIFT 6
138 u32 get_cpu_temp_grade(int *minc, int *maxc)
140 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
141 struct fuse_bank *bank = &ocotp->bank[1];
142 struct fuse_bank1_regs *fuse =
143 (struct fuse_bank1_regs *)bank->fuse_regs;
146 val = readl(&fuse->tester3);
147 val >>= OCOTP_TESTER3_TEMP_SHIFT;
151 if (val == TEMP_AUTOMOTIVE) {
154 } else if (val == TEMP_INDUSTRIAL) {
157 } else if (val == TEMP_EXTCOMMERCIAL) {
168 u32 get_cpu_rev(void)
170 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
172 u32 reg = readl(&ccm_anatop->digprog);
173 u32 type = (reg >> 16) & 0xff;
176 return (type << 12) | reg;
179 #ifdef CONFIG_REVISION_TAG
180 u32 __weak get_board_rev(void)
182 return get_cpu_rev();
186 /* enable all periherial can be accessed in nosec mode */
187 static void init_csu(void)
190 for (i = 0; i < CSU_NUM_REGS; i++)
191 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
194 static void imx_enet_mdio_fixup(void)
196 struct iomuxc_gpr_base_regs *gpr_regs =
197 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
200 * The management data input/output (MDIO) requires open-drain,
201 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
202 * this feature. So to TO1.1, need to enable open drain by setting
206 if (soc_rev() >= CHIP_REV_1_1) {
207 setbits_le32(&gpr_regs->gpr[0],
208 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
212 int arch_cpu_init(void)
217 /* Disable PDE bit of WMCR register */
218 imx_set_wdog_powerdown(false);
220 imx_enet_mdio_fixup();
222 #ifdef CONFIG_APBH_DMA
227 if (IS_ENABLED(CONFIG_IMX_RDC))
233 #ifdef CONFIG_SERIAL_TAG
234 void get_board_serial(struct tag_serialnr *serialnr)
236 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
237 struct fuse_bank *bank = &ocotp->bank[0];
238 struct fuse_bank0_regs *fuse =
239 (struct fuse_bank0_regs *)bank->fuse_regs;
241 serialnr->low = fuse->tester0;
242 serialnr->high = fuse->tester1;
246 #if defined(CONFIG_FEC_MXC)
247 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
249 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
250 struct fuse_bank *bank = &ocotp->bank[9];
251 struct fuse_bank9_regs *fuse =
252 (struct fuse_bank9_regs *)bank->fuse_regs;
255 u32 value = readl(&fuse->mac_addr1);
256 mac[0] = (value >> 8);
259 value = readl(&fuse->mac_addr0);
260 mac[2] = value >> 24;
261 mac[3] = value >> 16;
265 u32 value = readl(&fuse->mac_addr2);
266 mac[0] = value >> 24;
267 mac[1] = value >> 16;
271 value = readl(&fuse->mac_addr1);
272 mac[4] = value >> 24;
273 mac[5] = value >> 16;
278 #ifdef CONFIG_IMX_BOOTAUX
279 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
282 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
284 if (!boot_private_data)
287 stack = *(u32 *)boot_private_data;
288 pc = *(u32 *)(boot_private_data + 4);
290 /* Set the stack and pc to M4 bootROM */
291 writel(stack, M4_BOOTROM_BASE_ADDR);
292 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
295 clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
296 SRC_M4RCR_ENABLE_M4_MASK);
301 int arch_auxiliary_core_check_up(u32 core_id)
304 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
306 val = readl(&src_reg->m4rcr);
307 if (val & 0x00000001)
308 return 0; /* assert in reset */
314 void set_wdog_reset(struct wdog_regs *wdog)
316 u32 reg = readw(&wdog->wcr);
318 * Output WDOG_B signal to reset external pmic or POR_B decided by
319 * the board desgin. Without external reset, the peripherals/DDR/
320 * PMIC are not reset, that may cause system working abnormal.
322 reg = readw(&wdog->wcr);
325 * WDZST bit is write-once only bit. Align this bit in kernel,
326 * otherwise kernel code will have no chance to set this bit.
329 writew(reg, &wdog->wcr);
333 * cfg_val will be used for
334 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
335 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
336 * to SBMR1, which will determine the boot device.
338 const struct boot_mode soc_boot_modes[] = {
339 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
340 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
341 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
342 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
344 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
345 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
346 /* 4 bit bus width */
347 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
348 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
349 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
350 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
351 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
352 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
356 enum boot_device get_boot_device(void)
358 struct bootrom_sw_info **p =
359 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
361 enum boot_device boot_dev = SD1_BOOT;
362 u8 boot_type = (*p)->boot_dev_type;
363 u8 boot_instance = (*p)->boot_dev_instance;
367 boot_dev = boot_instance + SD1_BOOT;
370 boot_dev = boot_instance + MMC1_BOOT;
373 boot_dev = NAND_BOOT;
376 boot_dev = QSPI_BOOT;
379 boot_dev = WEIM_NOR_BOOT;
381 case BOOT_TYPE_SPINOR:
382 boot_dev = SPI_NOR_BOOT;
391 #ifdef CONFIG_ENV_IS_IN_MMC
392 __weak int board_mmc_get_env_dev(int devno)
394 return CONFIG_SYS_MMC_ENV_DEV;
397 int mmc_get_env_dev(void)
399 struct bootrom_sw_info **p =
400 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
401 int devno = (*p)->boot_dev_instance;
402 u8 boot_type = (*p)->boot_dev_type;
404 /* If not boot from sd/mmc, use default value */
405 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
406 return CONFIG_SYS_MMC_ENV_DEV;
408 return board_mmc_get_env_dev(devno);
414 #if !defined CONFIG_SPL_BUILD
415 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
417 "mrc p15, 0, r0, c1, c0, 1\n"
418 "orr r0, r0, #1 << 6\n"
419 "mcr p15, 0, r0, c1, c0, 1\n");
421 /* clock configuration. */