2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/boot_mode.h>
13 #include <asm/imx-common/dma.h>
14 #include <asm/imx-common/hab.h>
15 #include <asm/arch/crm_regs.h>
17 #include <imx_thermal.h>
19 #if defined(CONFIG_IMX_THERMAL)
20 static const struct imx_thermal_plat imx7_thermal_plat = {
21 .regs = (void *)ANATOP_BASE_ADDR,
26 U_BOOT_DEVICE(imx7_thermal) = {
27 .name = "imx_thermal",
28 .platdata = &imx7_thermal_plat,
32 #if defined(CONFIG_SECURE_BOOT)
33 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
40 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
41 * defines a 2-bit SPEED_GRADING
43 #define OCOTP_TESTER3_SPEED_SHIFT 8
44 #define OCOTP_TESTER3_SPEED_800MHZ 0
45 #define OCOTP_TESTER3_SPEED_850MHZ 1
46 #define OCOTP_TESTER3_SPEED_1GHZ 2
48 u32 get_cpu_speed_grade_hz(void)
50 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
51 struct fuse_bank *bank = &ocotp->bank[1];
52 struct fuse_bank1_regs *fuse =
53 (struct fuse_bank1_regs *)bank->fuse_regs;
56 val = readl(&fuse->tester3);
57 val >>= OCOTP_TESTER3_SPEED_SHIFT;
61 case OCOTP_TESTER3_SPEED_800MHZ:
63 case OCOTP_TESTER3_SPEED_850MHZ:
65 case OCOTP_TESTER3_SPEED_1GHZ:
72 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
73 * defines a 2-bit SPEED_GRADING
75 #define OCOTP_TESTER3_TEMP_SHIFT 6
77 u32 get_cpu_temp_grade(int *minc, int *maxc)
79 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
80 struct fuse_bank *bank = &ocotp->bank[1];
81 struct fuse_bank1_regs *fuse =
82 (struct fuse_bank1_regs *)bank->fuse_regs;
85 val = readl(&fuse->tester3);
86 val >>= OCOTP_TESTER3_TEMP_SHIFT;
90 if (val == TEMP_AUTOMOTIVE) {
93 } else if (val == TEMP_INDUSTRIAL) {
96 } else if (val == TEMP_EXTCOMMERCIAL) {
107 u32 get_cpu_rev(void)
109 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
111 u32 reg = readl(&ccm_anatop->digprog);
112 u32 type = (reg >> 16) & 0xff;
115 return (type << 12) | reg;
118 #ifdef CONFIG_REVISION_TAG
119 u32 __weak get_board_rev(void)
121 return get_cpu_rev();
125 int arch_cpu_init(void)
129 /* Disable PDE bit of WMCR register */
130 imx_set_wdog_powerdown(false);
132 #ifdef CONFIG_APBH_DMA
140 #ifdef CONFIG_SERIAL_TAG
141 void get_board_serial(struct tag_serialnr *serialnr)
143 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
144 struct fuse_bank *bank = &ocotp->bank[0];
145 struct fuse_bank0_regs *fuse =
146 (struct fuse_bank0_regs *)bank->fuse_regs;
148 serialnr->low = fuse->tester0;
149 serialnr->high = fuse->tester1;
153 #if defined(CONFIG_FEC_MXC)
154 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
156 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
157 struct fuse_bank *bank = &ocotp->bank[9];
158 struct fuse_bank9_regs *fuse =
159 (struct fuse_bank9_regs *)bank->fuse_regs;
162 u32 value = readl(&fuse->mac_addr1);
163 mac[0] = (value >> 8);
166 value = readl(&fuse->mac_addr0);
167 mac[2] = value >> 24;
168 mac[3] = value >> 16;
172 u32 value = readl(&fuse->mac_addr2);
173 mac[0] = value >> 24;
174 mac[1] = value >> 16;
178 value = readl(&fuse->mac_addr1);
179 mac[4] = value >> 24;
180 mac[5] = value >> 16;
185 void set_wdog_reset(struct wdog_regs *wdog)
187 u32 reg = readw(&wdog->wcr);
189 * Output WDOG_B signal to reset external pmic or POR_B decided by
190 * the board desgin. Without external reset, the peripherals/DDR/
191 * PMIC are not reset, that may cause system working abnormal.
193 reg = readw(&wdog->wcr);
196 * WDZST bit is write-once only bit. Align this bit in kernel,
197 * otherwise kernel code will have no chance to set this bit.
200 writew(reg, &wdog->wcr);
204 * cfg_val will be used for
205 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
206 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
207 * to SBMR1, which will determine the boot device.
209 const struct boot_mode soc_boot_modes[] = {
210 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
211 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
212 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
213 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
215 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
216 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
217 /* 4 bit bus width */
218 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
219 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
220 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
221 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
222 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
223 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
227 enum boot_device get_boot_device(void)
229 struct bootrom_sw_info **p =
230 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
232 enum boot_device boot_dev = SD1_BOOT;
233 u8 boot_type = (*p)->boot_dev_type;
234 u8 boot_instance = (*p)->boot_dev_instance;
238 boot_dev = boot_instance + SD1_BOOT;
241 boot_dev = boot_instance + MMC1_BOOT;
244 boot_dev = NAND_BOOT;
247 boot_dev = QSPI_BOOT;
250 boot_dev = WEIM_NOR_BOOT;
252 case BOOT_TYPE_SPINOR:
253 boot_dev = SPI_NOR_BOOT;
264 #if !defined CONFIG_SPL_BUILD
265 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
267 "mrc p15, 0, r0, c1, c0, 1\n"
268 "orr r0, r0, #1 << 6\n"
269 "mcr p15, 0, r0, c1, c0, 1\n");
271 /* clock configuration. */