2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/boot_mode.h>
13 #include <asm/imx-common/dma.h>
14 #include <asm/imx-common/hab.h>
15 #include <asm/arch/crm_regs.h>
17 #include <imx_thermal.h>
19 #if defined(CONFIG_IMX_THERMAL)
20 static const struct imx_thermal_plat imx7_thermal_plat = {
21 .regs = (void *)ANATOP_BASE_ADDR,
26 U_BOOT_DEVICE(imx7_thermal) = {
27 .name = "imx_thermal",
28 .platdata = &imx7_thermal_plat,
32 #if defined(CONFIG_SECURE_BOOT)
33 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
40 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
41 * defines a 2-bit SPEED_GRADING
43 #define OCOTP_TESTER3_SPEED_SHIFT 8
44 #define OCOTP_TESTER3_SPEED_800MHZ 0
45 #define OCOTP_TESTER3_SPEED_850MHZ 1
46 #define OCOTP_TESTER3_SPEED_1GHZ 2
48 u32 get_cpu_speed_grade_hz(void)
50 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
51 struct fuse_bank *bank = &ocotp->bank[1];
52 struct fuse_bank1_regs *fuse =
53 (struct fuse_bank1_regs *)bank->fuse_regs;
56 val = readl(&fuse->tester3);
57 val >>= OCOTP_TESTER3_SPEED_SHIFT;
61 case OCOTP_TESTER3_SPEED_800MHZ:
63 case OCOTP_TESTER3_SPEED_850MHZ:
65 case OCOTP_TESTER3_SPEED_1GHZ:
72 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
73 * defines a 2-bit SPEED_GRADING
75 #define OCOTP_TESTER3_TEMP_SHIFT 6
77 u32 get_cpu_temp_grade(int *minc, int *maxc)
79 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
80 struct fuse_bank *bank = &ocotp->bank[1];
81 struct fuse_bank1_regs *fuse =
82 (struct fuse_bank1_regs *)bank->fuse_regs;
85 val = readl(&fuse->tester3);
86 val >>= OCOTP_TESTER3_TEMP_SHIFT;
90 if (val == TEMP_AUTOMOTIVE) {
93 } else if (val == TEMP_INDUSTRIAL) {
96 } else if (val == TEMP_EXTCOMMERCIAL) {
107 u32 get_cpu_rev(void)
109 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
111 u32 reg = readl(&ccm_anatop->digprog);
112 u32 type = (reg >> 16) & 0xff;
115 return (type << 12) | reg;
118 #ifdef CONFIG_REVISION_TAG
119 u32 __weak get_board_rev(void)
121 return get_cpu_rev();
125 /* enable all periherial can be accessed in nosec mode */
126 static void init_csu(void)
129 for (i = 0; i < CSU_NUM_REGS; i++)
130 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
133 static void imx_enet_mdio_fixup(void)
135 struct iomuxc_gpr_base_regs *gpr_regs =
136 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
139 * The management data input/output (MDIO) requires open-drain,
140 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
141 * this feature. So to TO1.1, need to enable open drain by setting
145 if (soc_rev() >= CHIP_REV_1_1) {
146 setbits_le32(&gpr_regs->gpr[0],
147 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
151 int arch_cpu_init(void)
156 /* Disable PDE bit of WMCR register */
157 imx_set_wdog_powerdown(false);
159 imx_enet_mdio_fixup();
161 #ifdef CONFIG_APBH_DMA
169 #ifdef CONFIG_SERIAL_TAG
170 void get_board_serial(struct tag_serialnr *serialnr)
172 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
173 struct fuse_bank *bank = &ocotp->bank[0];
174 struct fuse_bank0_regs *fuse =
175 (struct fuse_bank0_regs *)bank->fuse_regs;
177 serialnr->low = fuse->tester0;
178 serialnr->high = fuse->tester1;
182 #if defined(CONFIG_FEC_MXC)
183 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
185 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
186 struct fuse_bank *bank = &ocotp->bank[9];
187 struct fuse_bank9_regs *fuse =
188 (struct fuse_bank9_regs *)bank->fuse_regs;
191 u32 value = readl(&fuse->mac_addr1);
192 mac[0] = (value >> 8);
195 value = readl(&fuse->mac_addr0);
196 mac[2] = value >> 24;
197 mac[3] = value >> 16;
201 u32 value = readl(&fuse->mac_addr2);
202 mac[0] = value >> 24;
203 mac[1] = value >> 16;
207 value = readl(&fuse->mac_addr1);
208 mac[4] = value >> 24;
209 mac[5] = value >> 16;
214 #ifdef CONFIG_IMX_BOOTAUX
215 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
218 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
220 if (!boot_private_data)
223 stack = *(u32 *)boot_private_data;
224 pc = *(u32 *)(boot_private_data + 4);
226 /* Set the stack and pc to M4 bootROM */
227 writel(stack, M4_BOOTROM_BASE_ADDR);
228 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
231 clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
232 SRC_M4RCR_ENABLE_M4_MASK);
237 int arch_auxiliary_core_check_up(u32 core_id)
240 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
242 val = readl(&src_reg->m4rcr);
243 if (val & 0x00000001)
244 return 0; /* assert in reset */
250 void set_wdog_reset(struct wdog_regs *wdog)
252 u32 reg = readw(&wdog->wcr);
254 * Output WDOG_B signal to reset external pmic or POR_B decided by
255 * the board desgin. Without external reset, the peripherals/DDR/
256 * PMIC are not reset, that may cause system working abnormal.
258 reg = readw(&wdog->wcr);
261 * WDZST bit is write-once only bit. Align this bit in kernel,
262 * otherwise kernel code will have no chance to set this bit.
265 writew(reg, &wdog->wcr);
269 * cfg_val will be used for
270 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
271 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
272 * to SBMR1, which will determine the boot device.
274 const struct boot_mode soc_boot_modes[] = {
275 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
276 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
277 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
278 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
280 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
281 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
282 /* 4 bit bus width */
283 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
284 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
285 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
286 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
287 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
288 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
292 enum boot_device get_boot_device(void)
294 struct bootrom_sw_info **p =
295 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
297 enum boot_device boot_dev = SD1_BOOT;
298 u8 boot_type = (*p)->boot_dev_type;
299 u8 boot_instance = (*p)->boot_dev_instance;
303 boot_dev = boot_instance + SD1_BOOT;
306 boot_dev = boot_instance + MMC1_BOOT;
309 boot_dev = NAND_BOOT;
312 boot_dev = QSPI_BOOT;
315 boot_dev = WEIM_NOR_BOOT;
317 case BOOT_TYPE_SPINOR:
318 boot_dev = SPI_NOR_BOOT;
327 #ifdef CONFIG_ENV_IS_IN_MMC
328 __weak int board_mmc_get_env_dev(int devno)
330 return CONFIG_SYS_MMC_ENV_DEV;
333 int mmc_get_env_dev(void)
335 struct bootrom_sw_info **p =
336 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
337 int devno = (*p)->boot_dev_instance;
338 u8 boot_type = (*p)->boot_dev_type;
340 /* If not boot from sd/mmc, use default value */
341 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
342 return CONFIG_SYS_MMC_ENV_DEV;
344 return board_mmc_get_env_dev(devno);
350 #if !defined CONFIG_SPL_BUILD
351 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
353 "mrc p15, 0, r0, c1, c0, 1\n"
354 "orr r0, r0, #1 << 6\n"
355 "mcr p15, 0, r0, c1, c0, 1\n");
357 /* clock configuration. */