2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h>
14 DECLARE_GLOBAL_DATA_PTR;
18 #ifdef CONFIG_FSL_ESDHC
19 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
20 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
21 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
22 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
28 static u32 get_fast_plat_clk(void)
30 return scg_clk_get_rate(SCG_NIC0_CLK);
33 static u32 get_slow_plat_clk(void)
35 return scg_clk_get_rate(SCG_NIC1_CLK);
38 static u32 get_ipg_clk(void)
40 return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
43 u32 get_lpuart_clk(void)
47 const u32 lpuart_array[] = {
58 const enum pcc_clk lpuart_pcc_clks[] = {
65 for (index = 0; index < 8; index++) {
66 if (lpuart_array[index] == LPUART_BASE)
70 if (index < 4 || index > 7)
73 return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
76 #ifdef CONFIG_SYS_LPI2C_IMX
77 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
79 /* Set parent to FIRC DIV2 clock */
80 const enum pcc_clk lpi2c_pcc_clks[] = {
87 if (i2c_num < 4 || i2c_num > 7)
91 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
92 pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
93 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
95 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
100 u32 imx_get_i2cclk(unsigned i2c_num)
102 const enum pcc_clk lpi2c_pcc_clks[] = {
109 if (i2c_num < 4 || i2c_num > 7)
112 return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
116 unsigned int mxc_get_clock(enum mxc_clock clk)
120 return scg_clk_get_rate(SCG_CORE_CLK);
122 return get_fast_plat_clk();
124 return get_slow_plat_clk();
126 return get_ipg_clk();
128 return pcc_clock_get_rate(PER_CLK_LPI2C4);
130 return get_lpuart_clk();
132 return pcc_clock_get_rate(PER_CLK_USDHC0);
134 return pcc_clock_get_rate(PER_CLK_USDHC1);
136 return scg_clk_get_rate(SCG_DDR_CLK);
138 printf("Unsupported mxc_clock %d\n", clk);
145 void init_clk_usdhc(u32 index)
149 /*Disable the clock before configure it */
150 pcc_clock_enable(PER_CLK_USDHC0, false);
152 /* 158MHz / 1 = 158MHz */
153 pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
154 pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
155 pcc_clock_enable(PER_CLK_USDHC0, true);
158 /*Disable the clock before configure it */
159 pcc_clock_enable(PER_CLK_USDHC1, false);
161 /* 158MHz / 1 = 158MHz */
162 pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
163 pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
164 pcc_clock_enable(PER_CLK_USDHC1, true);
167 printf("Invalid index for USDHC %d\n", index);
172 #ifdef CONFIG_MXC_OCOTP
174 #define OCOTP_CTRL_PCC1_SLOT (38)
175 #define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
177 void enable_ocotp_clk(unsigned char enable)
182 * Seems the OCOTP CLOCKs have been enabled at default,
183 * check its inuse flag
186 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
187 if (!(val & PCC_INUSE_MASK))
188 writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
190 val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
191 if (!(val & PCC_INUSE_MASK))
193 (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
197 void enable_usboh3_clk(unsigned char enable)
200 pcc_clock_enable(PER_CLK_USB0, false);
201 pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
202 pcc_clock_enable(PER_CLK_USB0, true);
204 #ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
205 if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
206 pcc_clock_enable(PER_CLK_USB1, false);
207 pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
208 pcc_clock_enable(PER_CLK_USB1, true);
212 pcc_clock_enable(PER_CLK_USB_PHY, true);
213 pcc_clock_enable(PER_CLK_USB_PL301, true);
215 pcc_clock_enable(PER_CLK_USB0, false);
216 pcc_clock_enable(PER_CLK_USB1, false);
217 pcc_clock_enable(PER_CLK_USB_PHY, false);
218 pcc_clock_enable(PER_CLK_USB_PL301, false);
222 static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
224 const enum pcc_clk lpuart_pcc_clks[] = {
231 if (index < 4 || index > 7)
234 #ifndef CONFIG_CLK_DEBUG
235 pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
237 pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
238 pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
241 static void init_clk_lpuart(void)
245 const u32 lpuart_array[] = {
256 for (i = 0; i < 8; i++) {
257 if (lpuart_array[i] == LPUART_BASE) {
263 lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
266 static void init_clk_rgpio2p(void)
268 /*Enable RGPIO2P1 clock */
269 pcc_clock_enable(PER_CLK_RGPIO2P1, true);
272 * Hard code to enable RGPIO2P0 clock since it is not
273 * in clock frame for A7 domain
275 writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
278 /* Configure PLL/PFD freq */
279 void clock_init(void)
282 * ROM has enabled clocks:
283 * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
284 * Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
285 * A7 side: SPLL PFD0 (scs selected, 413Mhz),
286 * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
287 * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
288 * IP BUS (NIC1_BUS) = 58.6Mhz
291 * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
293 * 3. Init the clocks of peripherals used in u-boot bu
294 * without set rate interface.The clocks for these
295 * peripherals are enabled in this intialization.
296 * 4.Other peripherals with set clock rate interface
297 * does not be set in this function.
302 scg_a7_soscdiv_init();
304 /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
305 scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
306 scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
307 scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
313 enable_usboh3_clk(1);
316 #ifdef CONFIG_SECURE_BOOT
317 void hab_caam_clock_enable(unsigned char enable)
320 pcc_clock_enable(PER_CLK_CAAM, true);
322 pcc_clock_enable(PER_CLK_CAAM, false);
327 * Dump some core clockes.
329 int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
333 freq = decode_pll(PLL_A7_SPLL);
334 printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
336 freq = decode_pll(PLL_A7_APLL);
337 printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
339 freq = decode_pll(PLL_USB);
340 printf("PLL_USB %8d MHz\n", freq / 1000000);
344 printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
345 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
346 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
347 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
348 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
349 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
350 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
351 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
352 printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
354 addr = (u32) clock_init;
355 printf("[%s] addr = 0x%08X\r\n", __func__, addr);
362 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,