3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
42 * printing to console doesn't work unless
43 * this code is executed from SPL
45 #define printf(fmt, args...)
49 static inline u32 __get_sys_clk_index(void)
53 * For ES1 the ROM code calibration of sys clock is not reliable
54 * due to hw issue. So, use hard-coded value. If this value is not
55 * correct for any board over-ride this function in board file
56 * From ES2.0 onwards you will get this information from
59 if (omap_revision() == OMAP4430_ES1_0)
60 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
62 /* SYS_CLKSEL - 1 to match the dpll param array indices */
63 ind = (readl(&prcm->cm_sys_clksel) &
64 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
69 u32 get_sys_clk_index(void)
70 __attribute__ ((weak, alias("__get_sys_clk_index")));
72 u32 get_sys_clk_freq(void)
74 u8 index = get_sys_clk_index();
75 return sys_clk_array[index];
78 static inline void do_bypass_dpll(u32 *const base)
80 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
82 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
83 CM_CLKMODE_DPLL_DPLL_EN_MASK,
84 DPLL_EN_FAST_RELOCK_BYPASS <<
85 CM_CLKMODE_DPLL_EN_SHIFT);
88 static inline void wait_for_bypass(u32 *const base)
90 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
92 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
94 printf("Bypassing DPLL failed %p\n", base);
98 static inline void do_lock_dpll(u32 *const base)
100 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
102 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
103 CM_CLKMODE_DPLL_DPLL_EN_MASK,
104 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
107 static inline void wait_for_lock(u32 *const base)
109 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
111 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
112 &dpll_regs->cm_idlest_dpll, LDELAY)) {
113 printf("DPLL locking failed for %p\n", base);
118 inline u32 check_for_lock(u32 *const base)
120 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
121 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
126 static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
130 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
132 temp = readl(&dpll_regs->cm_clksel_dpll);
134 if (check_for_lock(base)) {
136 * The Dpll has already been locked by rom code using CH.
137 * Check if M,N are matching with Ideal nominal opp values.
138 * If matches, skip the rest otherwise relock.
140 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
141 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
142 if ((M != (params->m)) || (N != (params->n))) {
143 debug("\n %s Dpll locked, but not for ideal M = %d,"
144 "N = %d values, current values are M = %d,"
145 "N= %d" , dpll, params->m, params->n,
148 /* Dpll locked with ideal values for nominal opps. */
149 debug("\n %s Dpll already locked with ideal"
150 "nominal opp values", dpll);
151 goto setup_post_dividers;
158 temp &= ~CM_CLKSEL_DPLL_M_MASK;
159 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
161 temp &= ~CM_CLKSEL_DPLL_N_MASK;
162 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
164 writel(temp, &dpll_regs->cm_clksel_dpll);
171 setup_post_dividers(base, params);
173 /* Wait till the DPLL locks */
178 u32 omap_ddr_clk(void)
180 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
181 const struct dpll_params *core_dpll_params;
183 omap_rev = omap_revision();
184 sys_clk_khz = get_sys_clk_freq() / 1000;
186 core_dpll_params = get_core_dpll_params();
188 debug("sys_clk %d\n ", sys_clk_khz * 1000);
190 /* Find Core DPLL locked frequency first */
191 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
192 (core_dpll_params->n + 1);
194 if (omap_rev < OMAP5430_ES1_0) {
196 * DDR frequency is PHY_ROOT_CLK/2
197 * PHY_ROOT_CLK = Fdpll/2/M2
202 * DDR frequency is PHY_ROOT_CLK
203 * PHY_ROOT_CLK = Fdpll/2/M2
208 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
209 ddr_clk *= 1000; /* convert to Hz */
210 debug("ddr_clk %d\n ", ddr_clk);
218 * Resulting MPU frequencies:
219 * 4430 ES1.0 : 600 MHz
220 * 4430 ES2.x : 792 MHz (OPP Turbo)
221 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
223 void configure_mpu_dpll(void)
225 const struct dpll_params *params;
226 struct dpll_regs *mpu_dpll_regs;
228 omap_rev = omap_revision();
231 * DCC and clock divider settings for 4460.
232 * DCC is required, if more than a certain frequency is required.
236 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
238 (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
239 bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
240 clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
241 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
242 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
243 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
244 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
245 CM_CLKSEL_DCC_EN_MASK);
248 params = get_mpu_dpll_params();
250 do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
251 debug("MPU DPLL locked\n");
254 static void setup_dplls(void)
257 const struct dpll_params *params;
259 debug("setup_dplls\n");
262 params = get_core_dpll_params(); /* default - safest */
264 * Do not lock the core DPLL now. Just set it up.
265 * Core DPLL will be locked after setting up EMIF
266 * using the FREQ_UPDATE method(freq_update_core())
268 do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
270 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
271 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
272 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
273 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
274 writel(temp, &prcm->cm_clksel_core);
275 debug("Core DPLL configured\n");
278 params = get_per_dpll_params();
279 do_setup_dpll(&prcm->cm_clkmode_dpll_per,
280 params, DPLL_LOCK, "per");
281 debug("PER DPLL locked\n");
284 configure_mpu_dpll();
287 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
288 static void setup_non_essential_dplls(void)
290 u32 sys_clk_khz, abe_ref_clk;
291 u32 sd_div, num, den;
292 const struct dpll_params *params;
294 sys_clk_khz = get_sys_clk_freq() / 1000;
297 clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
298 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
300 params = get_iva_dpll_params();
301 do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
305 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
306 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
307 * - where CLKINP is sys_clk in MHz
308 * Use CLKINP in KHz and adjust the denominator accordingly so
309 * that we have enough accuracy and at the same time no overflow
311 params = get_usb_dpll_params();
312 num = params->m * sys_clk_khz;
313 den = (params->n + 1) * 250 * 1000;
316 clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
317 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
318 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
320 /* Now setup the dpll with the regular function */
321 do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
323 /* Configure ABE dpll */
324 params = get_abe_dpll_params();
325 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
326 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
328 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
330 * We need to enable some additional options to achieve
331 * 196.608MHz from 32768 Hz
333 setbits_le32(&prcm->cm_clkmode_dpll_abe,
334 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
335 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
336 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
337 CM_CLKMODE_DPLL_REGM4XEN_MASK);
338 /* Spend 4 REFCLK cycles at each stage */
339 clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
340 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
341 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
344 /* Select the right reference clk */
345 clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
346 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
347 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
349 do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
353 void do_scale_tps62361(u32 reg, u32 volt_mv)
357 step = volt_mv - TPS62361_BASE_VOLT_MV;
360 temp = TPS62361_I2C_SLAVE_ADDR |
361 (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
362 (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
363 PRM_VC_VAL_BYPASS_VALID_BIT;
364 debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
366 writel(temp, &prcm->prm_vc_val_bypass);
367 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
368 &prcm->prm_vc_val_bypass, LDELAY)) {
369 puts("Scaling voltage failed for vdd_mpu from TPS\n");
373 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
375 u32 temp, offset_code;
376 u32 step = 12660; /* 12.66 mV represented in uV */
377 u32 offset = volt_mv;
379 /* convert to uV for better accuracy in the calculations */
382 if (omap_revision() == OMAP4430_ES1_0)
383 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
385 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
387 offset_code = (offset + step - 1) / step;
388 /* The code starts at 1 not 0 */
391 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
394 temp = SMPS_I2C_SLAVE_ADDR |
395 (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
396 (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
397 PRM_VC_VAL_BYPASS_VALID_BIT;
398 writel(temp, &prcm->prm_vc_val_bypass);
399 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
400 &prcm->prm_vc_val_bypass, LDELAY)) {
401 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
405 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
407 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
408 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
409 debug("Enable clock domain - %p\n", clkctrl_reg);
412 static inline void wait_for_clk_enable(u32 *clkctrl_addr)
414 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
417 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
418 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
420 clkctrl = readl(clkctrl_addr);
421 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
422 MODULE_CLKCTRL_IDLEST_SHIFT;
424 printf("Clock enable failed for 0x%p idlest 0x%x\n",
425 clkctrl_addr, clkctrl);
431 static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
434 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
435 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
436 debug("Enable clock module - %p\n", clkctrl_addr);
438 wait_for_clk_enable(clkctrl_addr);
441 void freq_update_core(void)
443 u32 freq_config1 = 0;
444 const struct dpll_params *core_dpll_params;
446 core_dpll_params = get_core_dpll_params();
447 /* Put EMIF clock domain in sw wakeup mode */
448 enable_clock_domain(&prcm->cm_memif_clkstctrl,
449 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
450 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
451 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
453 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
454 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
456 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
457 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
459 freq_config1 |= (core_dpll_params->m2 <<
460 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
461 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
463 writel(freq_config1, &prcm->cm_shadow_freq_config1);
464 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
465 &prcm->cm_shadow_freq_config1, LDELAY)) {
466 puts("FREQ UPDATE procedure failed!!");
470 /* Put EMIF clock domain back in hw auto mode */
471 enable_clock_domain(&prcm->cm_memif_clkstctrl,
472 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
473 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
474 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
477 void bypass_dpll(u32 *const base)
479 do_bypass_dpll(base);
480 wait_for_bypass(base);
483 void lock_dpll(u32 *const base)
489 void setup_clocks_for_console(void)
491 /* Do not add any spl_debug prints in this function */
492 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
493 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
494 CD_CLKCTRL_CLKTRCTRL_SHIFT);
496 /* Enable all UARTs - console will be on one of them */
497 clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
498 MODULE_CLKCTRL_MODULEMODE_MASK,
499 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
500 MODULE_CLKCTRL_MODULEMODE_SHIFT);
502 clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
503 MODULE_CLKCTRL_MODULEMODE_MASK,
504 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
505 MODULE_CLKCTRL_MODULEMODE_SHIFT);
507 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
508 MODULE_CLKCTRL_MODULEMODE_MASK,
509 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
510 MODULE_CLKCTRL_MODULEMODE_SHIFT);
512 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
513 MODULE_CLKCTRL_MODULEMODE_MASK,
514 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
515 MODULE_CLKCTRL_MODULEMODE_SHIFT);
517 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
518 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
519 CD_CLKCTRL_CLKTRCTRL_SHIFT);
522 void setup_sri2c(void)
524 u32 sys_clk_khz, cycles_hi, cycles_low, temp;
526 sys_clk_khz = get_sys_clk_freq() / 1000;
529 * Setup the dedicated I2C controller for Voltage Control
530 * I2C clk - high period 40% low period 60%
532 cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
533 cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
534 /* values to be set in register - less by 5 & 7 respectively */
537 temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
538 (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
539 writel(temp, &prcm->prm_vc_cfg_i2c_clk);
541 /* Disable high speed mode and all advanced features */
542 writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
545 void do_enable_clocks(u32 *const *clk_domains,
546 u32 *const *clk_modules_hw_auto,
547 u32 *const *clk_modules_explicit_en,
552 /* Put the clock domains in SW_WKUP mode */
553 for (i = 0; (i < max) && clk_domains[i]; i++) {
554 enable_clock_domain(clk_domains[i],
555 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
558 /* Clock modules that need to be put in HW_AUTO */
559 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
560 enable_clock_module(clk_modules_hw_auto[i],
561 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
565 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
566 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
567 enable_clock_module(clk_modules_explicit_en[i],
568 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
572 /* Put the clock domains in HW_AUTO mode now */
573 for (i = 0; (i < max) && clk_domains[i]; i++) {
574 enable_clock_domain(clk_domains[i],
575 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
581 switch (omap_hw_init_context()) {
582 case OMAP_INIT_CONTEXT_SPL:
583 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
584 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
585 enable_basic_clocks();
588 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
589 setup_non_essential_dplls();
590 enable_non_essential_clocks();
597 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
598 enable_basic_uboot_clocks();