3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/omap_common.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/utils.h>
23 #include <asm/omap_gpio.h>
26 #ifndef CONFIG_SPL_BUILD
28 * printing to console doesn't work unless
29 * this code is executed from SPL
31 #define printf(fmt, args...)
35 const u32 sys_clk_array[8] = {
36 12000000, /* 12 MHz */
37 20000000, /* 20 MHz */
38 16800000, /* 16.8 MHz */
39 19200000, /* 19.2 MHz */
40 26000000, /* 26 MHz */
41 27000000, /* 27 MHz */
42 38400000, /* 38.4 MHz */
45 static inline u32 __get_sys_clk_index(void)
49 * For ES1 the ROM code calibration of sys clock is not reliable
50 * due to hw issue. So, use hard-coded value. If this value is not
51 * correct for any board over-ride this function in board file
52 * From ES2.0 onwards you will get this information from
55 if (omap_revision() == OMAP4430_ES1_0)
56 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
58 /* SYS_CLKSEL - 1 to match the dpll param array indices */
59 ind = (readl((*prcm)->cm_sys_clksel) &
60 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
65 u32 get_sys_clk_index(void)
66 __attribute__ ((weak, alias("__get_sys_clk_index")));
68 u32 get_sys_clk_freq(void)
70 u8 index = get_sys_clk_index();
71 return sys_clk_array[index];
74 void setup_post_dividers(u32 const base, const struct dpll_params *params)
76 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
78 /* Setup post-dividers */
80 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
82 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
83 if (params->m4_h11 >= 0)
84 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
85 if (params->m5_h12 >= 0)
86 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
87 if (params->m6_h13 >= 0)
88 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
89 if (params->m7_h14 >= 0)
90 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
92 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
94 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
96 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
98 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
101 static inline void do_bypass_dpll(u32 const base)
103 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
105 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
106 CM_CLKMODE_DPLL_DPLL_EN_MASK,
107 DPLL_EN_FAST_RELOCK_BYPASS <<
108 CM_CLKMODE_DPLL_EN_SHIFT);
111 static inline void wait_for_bypass(u32 const base)
113 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
115 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
117 printf("Bypassing DPLL failed %x\n", base);
121 static inline void do_lock_dpll(u32 const base)
123 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
125 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
126 CM_CLKMODE_DPLL_DPLL_EN_MASK,
127 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
130 static inline void wait_for_lock(u32 const base)
132 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
134 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
135 &dpll_regs->cm_idlest_dpll, LDELAY)) {
136 printf("DPLL locking failed for %x\n", base);
141 inline u32 check_for_lock(u32 const base)
143 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
144 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
149 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
151 u32 sysclk_ind = get_sys_clk_index();
152 return &dpll_data->mpu[sysclk_ind];
155 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
157 u32 sysclk_ind = get_sys_clk_index();
158 return &dpll_data->core[sysclk_ind];
161 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
163 u32 sysclk_ind = get_sys_clk_index();
164 return &dpll_data->per[sysclk_ind];
167 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
169 u32 sysclk_ind = get_sys_clk_index();
170 return &dpll_data->iva[sysclk_ind];
173 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
175 u32 sysclk_ind = get_sys_clk_index();
176 return &dpll_data->usb[sysclk_ind];
179 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
181 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
182 u32 sysclk_ind = get_sys_clk_index();
183 return &dpll_data->abe[sysclk_ind];
185 return dpll_data->abe;
189 static const struct dpll_params *get_ddr_dpll_params
190 (struct dplls const *dpll_data)
192 u32 sysclk_ind = get_sys_clk_index();
196 return &dpll_data->ddr[sysclk_ind];
199 #ifdef CONFIG_DRIVER_TI_CPSW
200 static const struct dpll_params *get_gmac_dpll_params
201 (struct dplls const *dpll_data)
203 u32 sysclk_ind = get_sys_clk_index();
205 if (!dpll_data->gmac)
207 return &dpll_data->gmac[sysclk_ind];
211 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
215 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
220 temp = readl(&dpll_regs->cm_clksel_dpll);
222 if (check_for_lock(base)) {
224 * The Dpll has already been locked by rom code using CH.
225 * Check if M,N are matching with Ideal nominal opp values.
226 * If matches, skip the rest otherwise relock.
228 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
229 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
230 if ((M != (params->m)) || (N != (params->n))) {
231 debug("\n %s Dpll locked, but not for ideal M = %d,"
232 "N = %d values, current values are M = %d,"
233 "N= %d" , dpll, params->m, params->n,
236 /* Dpll locked with ideal values for nominal opps. */
237 debug("\n %s Dpll already locked with ideal"
238 "nominal opp values", dpll);
241 goto setup_post_dividers;
248 temp &= ~CM_CLKSEL_DPLL_M_MASK;
249 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
251 temp &= ~CM_CLKSEL_DPLL_N_MASK;
252 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
254 writel(temp, &dpll_regs->cm_clksel_dpll);
257 setup_post_dividers(base, params);
263 /* Wait till the DPLL locks */
268 u32 omap_ddr_clk(void)
270 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
271 const struct dpll_params *core_dpll_params;
273 omap_rev = omap_revision();
274 sys_clk_khz = get_sys_clk_freq() / 1000;
276 core_dpll_params = get_core_dpll_params(*dplls_data);
278 debug("sys_clk %d\n ", sys_clk_khz * 1000);
280 /* Find Core DPLL locked frequency first */
281 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
282 (core_dpll_params->n + 1);
284 if (omap_rev < OMAP5430_ES1_0) {
286 * DDR frequency is PHY_ROOT_CLK/2
287 * PHY_ROOT_CLK = Fdpll/2/M2
292 * DDR frequency is PHY_ROOT_CLK
293 * PHY_ROOT_CLK = Fdpll/2/M2
298 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
299 ddr_clk *= 1000; /* convert to Hz */
300 debug("ddr_clk %d\n ", ddr_clk);
308 * Resulting MPU frequencies:
309 * 4430 ES1.0 : 600 MHz
310 * 4430 ES2.x : 792 MHz (OPP Turbo)
311 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
313 void configure_mpu_dpll(void)
315 const struct dpll_params *params;
316 struct dpll_regs *mpu_dpll_regs;
318 omap_rev = omap_revision();
321 * DCC and clock divider settings for 4460.
322 * DCC is required, if more than a certain frequency is required.
326 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
328 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
329 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
330 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
331 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
332 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
333 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
334 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
335 CM_CLKSEL_DCC_EN_MASK);
338 params = get_mpu_dpll_params(*dplls_data);
340 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
341 debug("MPU DPLL locked\n");
344 #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
345 defined(CONFIG_USB_MUSB_OMAP2PLUS)
346 static void setup_usb_dpll(void)
348 const struct dpll_params *params;
349 u32 sys_clk_khz, sd_div, num, den;
351 sys_clk_khz = get_sys_clk_freq() / 1000;
354 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
355 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
356 * - where CLKINP is sys_clk in MHz
357 * Use CLKINP in KHz and adjust the denominator accordingly so
358 * that we have enough accuracy and at the same time no overflow
360 params = get_usb_dpll_params(*dplls_data);
361 num = params->m * sys_clk_khz;
362 den = (params->n + 1) * 250 * 1000;
365 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
366 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
367 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
369 /* Now setup the dpll with the regular function */
370 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
374 static void setup_dplls(void)
377 const struct dpll_params *params;
378 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
380 debug("setup_dplls\n");
383 params = get_core_dpll_params(*dplls_data); /* default - safest */
385 * Do not lock the core DPLL now. Just set it up.
386 * Core DPLL will be locked after setting up EMIF
387 * using the FREQ_UPDATE method(freq_update_core())
389 if (emif_sdram_type(readl(&emif->emif_sdram_config)) ==
390 EMIF_SDRAM_TYPE_LPDDR2)
391 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
392 DPLL_NO_LOCK, "core");
394 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
396 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
397 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
398 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
399 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
400 writel(temp, (*prcm)->cm_clksel_core);
401 debug("Core DPLL configured\n");
404 params = get_per_dpll_params(*dplls_data);
405 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
406 params, DPLL_LOCK, "per");
407 debug("PER DPLL locked\n");
410 configure_mpu_dpll();
412 #if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \
413 defined(CONFIG_USB_MUSB_OMAP2PLUS)
416 params = get_ddr_dpll_params(*dplls_data);
417 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
418 params, DPLL_LOCK, "ddr");
420 #ifdef CONFIG_DRIVER_TI_CPSW
421 params = get_gmac_dpll_params(*dplls_data);
422 do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
427 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
431 volt_offset -= pmic->base_offset;
433 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
436 * Offset codes 1-6 all give the base voltage in Palmas
437 * Offset code 0 switches OFF the SMPS
439 return offset_code + pmic->start_code;
442 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
445 u32 offset = volt_mv;
446 #ifndef CONFIG_DRA7XX
453 pmic->pmic_bus_init();
454 #ifndef CONFIG_DRA7XX
455 /* See if we can first get the GPIO if needed */
457 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
460 printf("%s: gpio %d request failed %d\n", __func__,
465 /* Pull the GPIO low to select SET0 register, while we program SET1 */
467 gpio_direction_output(pmic->gpio, 0);
469 /* convert to uV for better accuracy in the calculations */
472 offset_code = get_offset_code(offset, pmic);
474 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
477 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
478 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
479 #ifndef CONFIG_DRA7XX
481 gpio_direction_output(pmic->gpio, 1);
485 static u32 optimize_vcore_voltage(struct volts const *v)
493 switch (v->efuse.reg_bits) {
495 val = readw(v->efuse.reg);
498 val = readl(v->efuse.reg);
501 printf("Error: efuse 0x%08x bits=%d unknown\n",
502 v->efuse.reg, v->efuse.reg_bits);
507 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
508 v->efuse.reg, v->efuse.reg_bits, v->value);
512 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
513 __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
517 #ifdef CONFIG_IODELAY_RECALIBRATION
518 void __weak recalibrate_iodelay(void)
524 * Setup the voltages for the main SoC core power domains.
525 * We start with the maximum voltages allowed here, as set in the corresponding
526 * vcores_data struct, and then scale (usually down) to the fused values that
527 * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
529 * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
530 * compiled conditionally. Note that the new code writes the scaled (or zeroed)
531 * values back to the vcores_data struct for eventual reuse. Zero values mean
532 * that the corresponding rails are not controlled separately, and are not sent
535 void scale_vcores(struct vcores_data const *vcores)
537 #if defined(CONFIG_DRA7XX)
539 struct volts *pv = (struct volts *)vcores;
542 for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
543 debug("%d -> ", pv->value);
545 /* Handle non-empty members only */
546 pv->value = optimize_vcore_voltage(pv);
547 px = (struct volts *)vcores;
550 * Scan already handled non-empty members to see
551 * if we have a group and find the max voltage,
552 * which is set to the first occurance of the
553 * particular SMPS; the other group voltages are
557 if ((pv->pmic->i2c_slave_addr ==
558 px->pmic->i2c_slave_addr) &&
559 (pv->addr == px->addr)) {
560 /* Same PMIC, same SMPS */
561 if (pv->value > px->value)
562 px->value = pv->value;
570 debug("%d\n", pv->value);
574 debug("cor: %d\n", vcores->core.value);
575 do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
577 * IO delay recalibration should be done immediately after
578 * adjusting AVS voltages for VDD_CORE_L.
579 * Respective boards should call __recalibrate_iodelay()
580 * with proper mux, virtual and manual mode configurations.
582 #ifdef CONFIG_IODELAY_RECALIBRATION
583 recalibrate_iodelay();
586 debug("mpu: %d\n", vcores->mpu.value);
587 do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
588 /* Configure MPU ABB LDO after scale */
589 abb_setup(vcores->mpu.efuse.reg,
590 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
591 (*prcm)->prm_abbldo_mpu_setup,
592 (*prcm)->prm_abbldo_mpu_ctrl,
593 (*prcm)->prm_irqstatus_mpu_2,
594 vcores->mpu.abb_tx_done_mask,
597 /* The .mm member is not used for the DRA7xx */
599 debug("gpu: %d\n", vcores->gpu.value);
600 do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
601 /* Configure GPU ABB LDO after scale */
602 abb_setup(vcores->gpu.efuse.reg,
603 (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
604 (*prcm)->prm_abbldo_gpu_setup,
605 (*prcm)->prm_abbldo_gpu_ctrl,
606 (*prcm)->prm_irqstatus_mpu,
607 vcores->gpu.abb_tx_done_mask,
609 debug("eve: %d\n", vcores->eve.value);
610 do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
611 /* Configure EVE ABB LDO after scale */
612 abb_setup(vcores->eve.efuse.reg,
613 (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
614 (*prcm)->prm_abbldo_eve_setup,
615 (*prcm)->prm_abbldo_eve_ctrl,
616 (*prcm)->prm_irqstatus_mpu,
617 vcores->eve.abb_tx_done_mask,
619 debug("iva: %d\n", vcores->iva.value);
620 do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
621 /* Configure IVA ABB LDO after scale */
622 abb_setup(vcores->iva.efuse.reg,
623 (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
624 (*prcm)->prm_abbldo_iva_setup,
625 (*prcm)->prm_abbldo_iva_ctrl,
626 (*prcm)->prm_irqstatus_mpu,
627 vcores->iva.abb_tx_done_mask,
629 /* Might need udelay(1000) here if debug is enabled to see all prints */
633 val = optimize_vcore_voltage(&vcores->core);
634 do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
637 * IO delay recalibration should be done immediately after
638 * adjusting AVS voltages for VDD_CORE_L.
639 * Respective boards should call __recalibrate_iodelay()
640 * with proper mux, virtual and manual mode configurations.
642 #ifdef CONFIG_IODELAY_RECALIBRATION
643 recalibrate_iodelay();
646 val = optimize_vcore_voltage(&vcores->mpu);
647 do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
649 /* Configure MPU ABB LDO after scale */
650 abb_setup(vcores->mpu.efuse.reg,
651 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
652 (*prcm)->prm_abbldo_mpu_setup,
653 (*prcm)->prm_abbldo_mpu_ctrl,
654 (*prcm)->prm_irqstatus_mpu_2,
655 vcores->mpu.abb_tx_done_mask,
658 val = optimize_vcore_voltage(&vcores->mm);
659 do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
661 /* Configure MM ABB LDO after scale */
662 abb_setup(vcores->mm.efuse.reg,
663 (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
664 (*prcm)->prm_abbldo_mm_setup,
665 (*prcm)->prm_abbldo_mm_ctrl,
666 (*prcm)->prm_irqstatus_mpu,
667 vcores->mm.abb_tx_done_mask,
670 val = optimize_vcore_voltage(&vcores->gpu);
671 do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
673 val = optimize_vcore_voltage(&vcores->eve);
674 do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
676 val = optimize_vcore_voltage(&vcores->iva);
677 do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
681 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
683 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
684 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
685 debug("Enable clock domain - %x\n", clkctrl_reg);
688 static inline void disable_clock_domain(u32 const clkctrl_reg)
690 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
691 CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
692 CD_CLKCTRL_CLKTRCTRL_SHIFT);
693 debug("Disable clock domain - %x\n", clkctrl_reg);
696 static inline void wait_for_clk_enable(u32 clkctrl_addr)
698 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
701 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
702 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
704 clkctrl = readl(clkctrl_addr);
705 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
706 MODULE_CLKCTRL_IDLEST_SHIFT;
708 printf("Clock enable failed for 0x%x idlest 0x%x\n",
709 clkctrl_addr, clkctrl);
715 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
718 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
719 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
720 debug("Enable clock module - %x\n", clkctrl_addr);
722 wait_for_clk_enable(clkctrl_addr);
725 static inline void wait_for_clk_disable(u32 clkctrl_addr)
727 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
730 while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
731 clkctrl = readl(clkctrl_addr);
732 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
733 MODULE_CLKCTRL_IDLEST_SHIFT;
735 printf("Clock disable failed for 0x%x idlest 0x%x\n",
736 clkctrl_addr, clkctrl);
742 static inline void disable_clock_module(u32 const clkctrl_addr,
743 u32 wait_for_disable)
745 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
746 MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
747 MODULE_CLKCTRL_MODULEMODE_SHIFT);
748 debug("Disable clock module - %x\n", clkctrl_addr);
749 if (wait_for_disable)
750 wait_for_clk_disable(clkctrl_addr);
753 void freq_update_core(void)
755 u32 freq_config1 = 0;
756 const struct dpll_params *core_dpll_params;
757 u32 omap_rev = omap_revision();
759 core_dpll_params = get_core_dpll_params(*dplls_data);
760 /* Put EMIF clock domain in sw wakeup mode */
761 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
762 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
763 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
764 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
766 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
767 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
769 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
770 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
772 freq_config1 |= (core_dpll_params->m2 <<
773 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
774 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
776 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
777 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
778 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
779 puts("FREQ UPDATE procedure failed!!");
784 * Putting EMIF in HW_AUTO is seen to be causing issues with
785 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
786 * in OMAP5430 ES1.0 silicon
788 if (omap_rev != OMAP5430_ES1_0) {
789 /* Put EMIF clock domain back in hw auto mode */
790 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
791 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
792 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
793 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
797 void bypass_dpll(u32 const base)
799 do_bypass_dpll(base);
800 wait_for_bypass(base);
803 void lock_dpll(u32 const base)
809 static void setup_clocks_for_console(void)
811 /* Do not add any spl_debug prints in this function */
812 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
813 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
814 CD_CLKCTRL_CLKTRCTRL_SHIFT);
816 /* Enable all UARTs - console will be on one of them */
817 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
818 MODULE_CLKCTRL_MODULEMODE_MASK,
819 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
820 MODULE_CLKCTRL_MODULEMODE_SHIFT);
822 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
823 MODULE_CLKCTRL_MODULEMODE_MASK,
824 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
825 MODULE_CLKCTRL_MODULEMODE_SHIFT);
827 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
828 MODULE_CLKCTRL_MODULEMODE_MASK,
829 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
830 MODULE_CLKCTRL_MODULEMODE_SHIFT);
832 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
833 MODULE_CLKCTRL_MODULEMODE_MASK,
834 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
835 MODULE_CLKCTRL_MODULEMODE_SHIFT);
837 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
838 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
839 CD_CLKCTRL_CLKTRCTRL_SHIFT);
842 void do_enable_clocks(u32 const *clk_domains,
843 u32 const *clk_modules_hw_auto,
844 u32 const *clk_modules_explicit_en,
849 /* Put the clock domains in SW_WKUP mode */
850 for (i = 0; (i < max) && clk_domains[i]; i++) {
851 enable_clock_domain(clk_domains[i],
852 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
855 /* Clock modules that need to be put in HW_AUTO */
856 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
857 enable_clock_module(clk_modules_hw_auto[i],
858 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
862 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
863 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
864 enable_clock_module(clk_modules_explicit_en[i],
865 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
869 /* Put the clock domains in HW_AUTO mode now */
870 for (i = 0; (i < max) && clk_domains[i]; i++) {
871 enable_clock_domain(clk_domains[i],
872 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
876 void do_disable_clocks(u32 const *clk_domains,
877 u32 const *clk_modules_disable,
883 /* Clock modules that need to be put in SW_DISABLE */
884 for (i = 0; (i < max) && clk_modules_disable[i]; i++)
885 disable_clock_module(clk_modules_disable[i],
888 /* Put the clock domains in SW_SLEEP mode */
889 for (i = 0; (i < max) && clk_domains[i]; i++)
890 disable_clock_domain(clk_domains[i]);
894 * setup_early_clocks() - Setup early clocks needed for SoC
896 * Setup clocks for console, SPL basic initialization clocks and initialize
897 * the timer. This is invoked prior prcm_init.
899 void setup_early_clocks(void)
901 switch (omap_hw_init_context()) {
902 case OMAP_INIT_CONTEXT_SPL:
903 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
904 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
905 setup_clocks_for_console();
906 enable_basic_clocks();
914 switch (omap_hw_init_context()) {
915 case OMAP_INIT_CONTEXT_SPL:
916 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
917 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
918 scale_vcores(*omap_vcores);
920 setup_warmreset_time();
926 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
927 enable_basic_uboot_clocks();
930 void gpi2c_init(void)
932 static int gpi2c = 1;
935 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
936 CONFIG_SYS_OMAP24_I2C_SLAVE);