3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
42 * printing to console doesn't work unless
43 * this code is executed from SPL
45 #define printf(fmt, args...)
49 static inline u32 __get_sys_clk_index(void)
53 * For ES1 the ROM code calibration of sys clock is not reliable
54 * due to hw issue. So, use hard-coded value. If this value is not
55 * correct for any board over-ride this function in board file
56 * From ES2.0 onwards you will get this information from
59 if (omap_revision() == OMAP4430_ES1_0)
60 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
62 /* SYS_CLKSEL - 1 to match the dpll param array indices */
63 ind = (readl(&prcm->cm_sys_clksel) &
64 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
69 u32 get_sys_clk_index(void)
70 __attribute__ ((weak, alias("__get_sys_clk_index")));
72 u32 get_sys_clk_freq(void)
74 u8 index = get_sys_clk_index();
75 return sys_clk_array[index];
78 static inline void do_bypass_dpll(u32 *const base)
80 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
82 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
83 CM_CLKMODE_DPLL_DPLL_EN_MASK,
84 DPLL_EN_FAST_RELOCK_BYPASS <<
85 CM_CLKMODE_DPLL_EN_SHIFT);
88 static inline void wait_for_bypass(u32 *const base)
90 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
92 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
94 printf("Bypassing DPLL failed %p\n", base);
98 static inline void do_lock_dpll(u32 *const base)
100 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
102 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
103 CM_CLKMODE_DPLL_DPLL_EN_MASK,
104 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
107 static inline void wait_for_lock(u32 *const base)
109 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
111 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
112 &dpll_regs->cm_idlest_dpll, LDELAY)) {
113 printf("DPLL locking failed for %p\n", base);
118 inline u32 check_for_lock(u32 *const base)
120 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
121 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
126 static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
130 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
132 temp = readl(&dpll_regs->cm_clksel_dpll);
134 if (check_for_lock(base)) {
136 * The Dpll has already been locked by rom code using CH.
137 * Check if M,N are matching with Ideal nominal opp values.
138 * If matches, skip the rest otherwise relock.
140 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
141 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
142 if ((M != (params->m)) || (N != (params->n))) {
143 debug("\n %s Dpll locked, but not for ideal M = %d,"
144 "N = %d values, current values are M = %d,"
145 "N= %d" , dpll, params->m, params->n,
148 /* Dpll locked with ideal values for nominal opps. */
149 debug("\n %s Dpll already locked with ideal"
150 "nominal opp values", dpll);
151 goto setup_post_dividers;
158 temp &= ~CM_CLKSEL_DPLL_M_MASK;
159 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
161 temp &= ~CM_CLKSEL_DPLL_N_MASK;
162 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
164 writel(temp, &dpll_regs->cm_clksel_dpll);
171 setup_post_dividers(base, params);
173 /* Wait till the DPLL locks */
178 u32 omap_ddr_clk(void)
180 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
181 const struct dpll_params *core_dpll_params;
183 omap_rev = omap_revision();
184 sys_clk_khz = get_sys_clk_freq() / 1000;
186 core_dpll_params = get_core_dpll_params();
188 debug("sys_clk %d\n ", sys_clk_khz * 1000);
190 /* Find Core DPLL locked frequency first */
191 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
192 (core_dpll_params->n + 1);
194 if (omap_rev < OMAP5430_ES1_0) {
196 * DDR frequency is PHY_ROOT_CLK/2
197 * PHY_ROOT_CLK = Fdpll/2/M2
202 * DDR frequency is PHY_ROOT_CLK
203 * PHY_ROOT_CLK = Fdpll/2/M2
208 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
209 ddr_clk *= 1000; /* convert to Hz */
210 debug("ddr_clk %d\n ", ddr_clk);
218 * Resulting MPU frequencies:
219 * 4430 ES1.0 : 600 MHz
220 * 4430 ES2.x : 792 MHz (OPP Turbo)
221 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
223 void configure_mpu_dpll(void)
225 const struct dpll_params *params;
226 struct dpll_regs *mpu_dpll_regs;
228 omap_rev = omap_revision();
231 * DCC and clock divider settings for 4460.
232 * DCC is required, if more than a certain frequency is required.
236 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
238 (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
239 bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
240 clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
241 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
242 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
243 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
244 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
245 CM_CLKSEL_DCC_EN_MASK);
248 params = get_mpu_dpll_params();
250 do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
251 debug("MPU DPLL locked\n");
254 #ifdef CONFIG_USB_EHCI_OMAP
255 static void setup_usb_dpll(void)
257 const struct dpll_params *params;
258 u32 sys_clk_khz, sd_div, num, den;
260 sys_clk_khz = get_sys_clk_freq() / 1000;
263 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
264 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
265 * - where CLKINP is sys_clk in MHz
266 * Use CLKINP in KHz and adjust the denominator accordingly so
267 * that we have enough accuracy and at the same time no overflow
269 params = get_usb_dpll_params();
270 num = params->m * sys_clk_khz;
271 den = (params->n + 1) * 250 * 1000;
274 clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
275 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
276 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
278 /* Now setup the dpll with the regular function */
279 do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
283 static void setup_dplls(void)
286 const struct dpll_params *params;
288 debug("setup_dplls\n");
291 params = get_core_dpll_params(); /* default - safest */
293 * Do not lock the core DPLL now. Just set it up.
294 * Core DPLL will be locked after setting up EMIF
295 * using the FREQ_UPDATE method(freq_update_core())
297 do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
299 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
300 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
301 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
302 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
303 writel(temp, &prcm->cm_clksel_core);
304 debug("Core DPLL configured\n");
307 params = get_per_dpll_params();
308 do_setup_dpll(&prcm->cm_clkmode_dpll_per,
309 params, DPLL_LOCK, "per");
310 debug("PER DPLL locked\n");
313 configure_mpu_dpll();
315 #ifdef CONFIG_USB_EHCI_OMAP
320 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
321 static void setup_non_essential_dplls(void)
323 u32 sys_clk_khz, abe_ref_clk;
324 const struct dpll_params *params;
326 sys_clk_khz = get_sys_clk_freq() / 1000;
329 clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
330 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
332 params = get_iva_dpll_params();
333 do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
335 /* Configure ABE dpll */
336 params = get_abe_dpll_params();
337 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
338 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
340 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
342 * We need to enable some additional options to achieve
343 * 196.608MHz from 32768 Hz
345 setbits_le32(&prcm->cm_clkmode_dpll_abe,
346 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
347 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
348 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
349 CM_CLKMODE_DPLL_REGM4XEN_MASK);
350 /* Spend 4 REFCLK cycles at each stage */
351 clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
352 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
353 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
356 /* Select the right reference clk */
357 clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
358 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
359 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
361 do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
365 void do_scale_tps62361(u32 reg, u32 volt_mv)
369 step = volt_mv - TPS62361_BASE_VOLT_MV;
372 temp = TPS62361_I2C_SLAVE_ADDR |
373 (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
374 (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
375 PRM_VC_VAL_BYPASS_VALID_BIT;
376 debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
378 writel(temp, &prcm->prm_vc_val_bypass);
379 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
380 &prcm->prm_vc_val_bypass, LDELAY)) {
381 puts("Scaling voltage failed for vdd_mpu from TPS\n");
385 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
387 u32 temp, offset_code;
388 u32 step = 12660; /* 12.66 mV represented in uV */
389 u32 offset = volt_mv;
391 /* convert to uV for better accuracy in the calculations */
394 if (omap_revision() == OMAP4430_ES1_0)
395 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
397 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
399 offset_code = (offset + step - 1) / step;
400 /* The code starts at 1 not 0 */
403 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
406 temp = SMPS_I2C_SLAVE_ADDR |
407 (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
408 (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
409 PRM_VC_VAL_BYPASS_VALID_BIT;
410 writel(temp, &prcm->prm_vc_val_bypass);
411 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
412 &prcm->prm_vc_val_bypass, LDELAY)) {
413 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
417 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
419 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
420 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
421 debug("Enable clock domain - %p\n", clkctrl_reg);
424 static inline void wait_for_clk_enable(u32 *clkctrl_addr)
426 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
429 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
430 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
432 clkctrl = readl(clkctrl_addr);
433 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
434 MODULE_CLKCTRL_IDLEST_SHIFT;
436 printf("Clock enable failed for 0x%p idlest 0x%x\n",
437 clkctrl_addr, clkctrl);
443 static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
446 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
447 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
448 debug("Enable clock module - %p\n", clkctrl_addr);
450 wait_for_clk_enable(clkctrl_addr);
453 void freq_update_core(void)
455 u32 freq_config1 = 0;
456 const struct dpll_params *core_dpll_params;
458 core_dpll_params = get_core_dpll_params();
459 /* Put EMIF clock domain in sw wakeup mode */
460 enable_clock_domain(&prcm->cm_memif_clkstctrl,
461 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
462 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
463 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
465 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
466 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
468 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
469 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
471 freq_config1 |= (core_dpll_params->m2 <<
472 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
473 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
475 writel(freq_config1, &prcm->cm_shadow_freq_config1);
476 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
477 &prcm->cm_shadow_freq_config1, LDELAY)) {
478 puts("FREQ UPDATE procedure failed!!");
482 /* Put EMIF clock domain back in hw auto mode */
483 enable_clock_domain(&prcm->cm_memif_clkstctrl,
484 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
485 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
486 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
489 void bypass_dpll(u32 *const base)
491 do_bypass_dpll(base);
492 wait_for_bypass(base);
495 void lock_dpll(u32 *const base)
501 void setup_clocks_for_console(void)
503 /* Do not add any spl_debug prints in this function */
504 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
505 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
506 CD_CLKCTRL_CLKTRCTRL_SHIFT);
508 /* Enable all UARTs - console will be on one of them */
509 clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
510 MODULE_CLKCTRL_MODULEMODE_MASK,
511 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
512 MODULE_CLKCTRL_MODULEMODE_SHIFT);
514 clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
515 MODULE_CLKCTRL_MODULEMODE_MASK,
516 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
517 MODULE_CLKCTRL_MODULEMODE_SHIFT);
519 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
520 MODULE_CLKCTRL_MODULEMODE_MASK,
521 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
522 MODULE_CLKCTRL_MODULEMODE_SHIFT);
524 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
525 MODULE_CLKCTRL_MODULEMODE_MASK,
526 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
527 MODULE_CLKCTRL_MODULEMODE_SHIFT);
529 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
530 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
531 CD_CLKCTRL_CLKTRCTRL_SHIFT);
534 void setup_sri2c(void)
536 u32 sys_clk_khz, cycles_hi, cycles_low, temp;
538 sys_clk_khz = get_sys_clk_freq() / 1000;
541 * Setup the dedicated I2C controller for Voltage Control
542 * I2C clk - high period 40% low period 60%
544 cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
545 cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
546 /* values to be set in register - less by 5 & 7 respectively */
549 temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
550 (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
551 writel(temp, &prcm->prm_vc_cfg_i2c_clk);
553 /* Disable high speed mode and all advanced features */
554 writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
557 void do_enable_clocks(u32 *const *clk_domains,
558 u32 *const *clk_modules_hw_auto,
559 u32 *const *clk_modules_explicit_en,
564 /* Put the clock domains in SW_WKUP mode */
565 for (i = 0; (i < max) && clk_domains[i]; i++) {
566 enable_clock_domain(clk_domains[i],
567 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
570 /* Clock modules that need to be put in HW_AUTO */
571 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
572 enable_clock_module(clk_modules_hw_auto[i],
573 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
577 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
578 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
579 enable_clock_module(clk_modules_explicit_en[i],
580 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
584 /* Put the clock domains in HW_AUTO mode now */
585 for (i = 0; (i < max) && clk_domains[i]; i++) {
586 enable_clock_domain(clk_domains[i],
587 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
593 switch (omap_hw_init_context()) {
594 case OMAP_INIT_CONTEXT_SPL:
595 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
596 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
597 enable_basic_clocks();
600 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
601 setup_non_essential_dplls();
602 enable_non_essential_clocks();
609 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
610 enable_basic_uboot_clocks();