3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/omap_common.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/utils.h>
23 #include <asm/omap_gpio.h>
26 #ifndef CONFIG_SPL_BUILD
28 * printing to console doesn't work unless
29 * this code is executed from SPL
31 #define printf(fmt, args...)
35 const u32 sys_clk_array[8] = {
36 12000000, /* 12 MHz */
37 20000000, /* 20 MHz */
38 16800000, /* 16.8 MHz */
39 19200000, /* 19.2 MHz */
40 26000000, /* 26 MHz */
41 27000000, /* 27 MHz */
42 38400000, /* 38.4 MHz */
45 static inline u32 __get_sys_clk_index(void)
49 * For ES1 the ROM code calibration of sys clock is not reliable
50 * due to hw issue. So, use hard-coded value. If this value is not
51 * correct for any board over-ride this function in board file
52 * From ES2.0 onwards you will get this information from
55 if (omap_revision() == OMAP4430_ES1_0)
56 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
58 /* SYS_CLKSEL - 1 to match the dpll param array indices */
59 ind = (readl((*prcm)->cm_sys_clksel) &
60 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
65 u32 get_sys_clk_index(void)
66 __attribute__ ((weak, alias("__get_sys_clk_index")));
68 u32 get_sys_clk_freq(void)
70 u8 index = get_sys_clk_index();
71 return sys_clk_array[index];
74 void setup_post_dividers(u32 const base, const struct dpll_params *params)
76 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
78 /* Setup post-dividers */
80 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
82 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
83 if (params->m4_h11 >= 0)
84 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
85 if (params->m5_h12 >= 0)
86 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
87 if (params->m6_h13 >= 0)
88 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
89 if (params->m7_h14 >= 0)
90 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
92 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
94 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
96 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
98 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
101 static inline void do_bypass_dpll(u32 const base)
103 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
105 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
106 CM_CLKMODE_DPLL_DPLL_EN_MASK,
107 DPLL_EN_FAST_RELOCK_BYPASS <<
108 CM_CLKMODE_DPLL_EN_SHIFT);
111 static inline void wait_for_bypass(u32 const base)
113 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
115 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
117 printf("Bypassing DPLL failed %x\n", base);
121 static inline void do_lock_dpll(u32 const base)
123 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
125 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
126 CM_CLKMODE_DPLL_DPLL_EN_MASK,
127 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
130 static inline void wait_for_lock(u32 const base)
132 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
134 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
135 &dpll_regs->cm_idlest_dpll, LDELAY)) {
136 printf("DPLL locking failed for %x\n", base);
141 inline u32 check_for_lock(u32 const base)
143 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
144 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
149 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
151 u32 sysclk_ind = get_sys_clk_index();
152 return &dpll_data->mpu[sysclk_ind];
155 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
157 u32 sysclk_ind = get_sys_clk_index();
158 return &dpll_data->core[sysclk_ind];
161 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
163 u32 sysclk_ind = get_sys_clk_index();
164 return &dpll_data->per[sysclk_ind];
167 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
169 u32 sysclk_ind = get_sys_clk_index();
170 return &dpll_data->iva[sysclk_ind];
173 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
175 u32 sysclk_ind = get_sys_clk_index();
176 return &dpll_data->usb[sysclk_ind];
179 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
181 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
182 u32 sysclk_ind = get_sys_clk_index();
183 return &dpll_data->abe[sysclk_ind];
185 return dpll_data->abe;
189 static const struct dpll_params *get_ddr_dpll_params
190 (struct dplls const *dpll_data)
192 u32 sysclk_ind = get_sys_clk_index();
196 return &dpll_data->ddr[sysclk_ind];
199 #ifdef CONFIG_DRIVER_TI_CPSW
200 static const struct dpll_params *get_gmac_dpll_params
201 (struct dplls const *dpll_data)
203 u32 sysclk_ind = get_sys_clk_index();
205 if (!dpll_data->gmac)
207 return &dpll_data->gmac[sysclk_ind];
211 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
215 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
220 temp = readl(&dpll_regs->cm_clksel_dpll);
222 if (check_for_lock(base)) {
224 * The Dpll has already been locked by rom code using CH.
225 * Check if M,N are matching with Ideal nominal opp values.
226 * If matches, skip the rest otherwise relock.
228 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
229 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
230 if ((M != (params->m)) || (N != (params->n))) {
231 debug("\n %s Dpll locked, but not for ideal M = %d,"
232 "N = %d values, current values are M = %d,"
233 "N= %d" , dpll, params->m, params->n,
236 /* Dpll locked with ideal values for nominal opps. */
237 debug("\n %s Dpll already locked with ideal"
238 "nominal opp values", dpll);
239 goto setup_post_dividers;
246 temp &= ~CM_CLKSEL_DPLL_M_MASK;
247 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
249 temp &= ~CM_CLKSEL_DPLL_N_MASK;
250 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
252 writel(temp, &dpll_regs->cm_clksel_dpll);
259 setup_post_dividers(base, params);
261 /* Wait till the DPLL locks */
266 u32 omap_ddr_clk(void)
268 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
269 const struct dpll_params *core_dpll_params;
271 omap_rev = omap_revision();
272 sys_clk_khz = get_sys_clk_freq() / 1000;
274 core_dpll_params = get_core_dpll_params(*dplls_data);
276 debug("sys_clk %d\n ", sys_clk_khz * 1000);
278 /* Find Core DPLL locked frequency first */
279 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
280 (core_dpll_params->n + 1);
282 if (omap_rev < OMAP5430_ES1_0) {
284 * DDR frequency is PHY_ROOT_CLK/2
285 * PHY_ROOT_CLK = Fdpll/2/M2
290 * DDR frequency is PHY_ROOT_CLK
291 * PHY_ROOT_CLK = Fdpll/2/M2
296 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
297 ddr_clk *= 1000; /* convert to Hz */
298 debug("ddr_clk %d\n ", ddr_clk);
306 * Resulting MPU frequencies:
307 * 4430 ES1.0 : 600 MHz
308 * 4430 ES2.x : 792 MHz (OPP Turbo)
309 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
311 void configure_mpu_dpll(void)
313 const struct dpll_params *params;
314 struct dpll_regs *mpu_dpll_regs;
316 omap_rev = omap_revision();
319 * DCC and clock divider settings for 4460.
320 * DCC is required, if more than a certain frequency is required.
324 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
326 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
327 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
328 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
329 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
330 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
331 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
332 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
333 CM_CLKSEL_DCC_EN_MASK);
336 params = get_mpu_dpll_params(*dplls_data);
338 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
339 debug("MPU DPLL locked\n");
342 #ifdef CONFIG_USB_EHCI_OMAP
343 static void setup_usb_dpll(void)
345 const struct dpll_params *params;
346 u32 sys_clk_khz, sd_div, num, den;
348 sys_clk_khz = get_sys_clk_freq() / 1000;
351 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
352 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
353 * - where CLKINP is sys_clk in MHz
354 * Use CLKINP in KHz and adjust the denominator accordingly so
355 * that we have enough accuracy and at the same time no overflow
357 params = get_usb_dpll_params(*dplls_data);
358 num = params->m * sys_clk_khz;
359 den = (params->n + 1) * 250 * 1000;
362 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
363 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
364 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
366 /* Now setup the dpll with the regular function */
367 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
371 static void setup_dplls(void)
374 const struct dpll_params *params;
376 debug("setup_dplls\n");
379 params = get_core_dpll_params(*dplls_data); /* default - safest */
381 * Do not lock the core DPLL now. Just set it up.
382 * Core DPLL will be locked after setting up EMIF
383 * using the FREQ_UPDATE method(freq_update_core())
385 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
386 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
387 DPLL_NO_LOCK, "core");
389 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
391 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
392 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
393 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
394 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
395 writel(temp, (*prcm)->cm_clksel_core);
396 debug("Core DPLL configured\n");
399 params = get_per_dpll_params(*dplls_data);
400 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
401 params, DPLL_LOCK, "per");
402 debug("PER DPLL locked\n");
405 configure_mpu_dpll();
407 #ifdef CONFIG_USB_EHCI_OMAP
410 params = get_ddr_dpll_params(*dplls_data);
411 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
412 params, DPLL_LOCK, "ddr");
414 #ifdef CONFIG_DRIVER_TI_CPSW
415 params = get_gmac_dpll_params(*dplls_data);
416 do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
421 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
422 static void setup_non_essential_dplls(void)
425 const struct dpll_params *params;
428 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
429 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
431 params = get_iva_dpll_params(*dplls_data);
432 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
434 /* Configure ABE dpll */
435 params = get_abe_dpll_params(*dplls_data);
436 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
437 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
439 if (omap_revision() == DRA752_ES1_0)
440 /* Select the sys clk for dpll_abe */
441 clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
442 CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
443 CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
445 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
447 * We need to enable some additional options to achieve
448 * 196.608MHz from 32768 Hz
450 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
451 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
452 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
453 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
454 CM_CLKMODE_DPLL_REGM4XEN_MASK);
455 /* Spend 4 REFCLK cycles at each stage */
456 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
457 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
458 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
461 /* Select the right reference clk */
462 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
463 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
464 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
466 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
470 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
474 volt_offset -= pmic->base_offset;
476 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
479 * Offset codes 1-6 all give the base voltage in Palmas
480 * Offset code 0 switches OFF the SMPS
482 return offset_code + pmic->start_code;
485 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
488 u32 offset = volt_mv;
494 pmic->pmic_bus_init();
495 /* See if we can first get the GPIO if needed */
497 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
500 printf("%s: gpio %d request failed %d\n", __func__,
505 /* Pull the GPIO low to select SET0 register, while we program SET1 */
507 gpio_direction_output(pmic->gpio, 0);
509 /* convert to uV for better accuracy in the calculations */
512 offset_code = get_offset_code(offset, pmic);
514 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
517 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
518 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
521 gpio_direction_output(pmic->gpio, 1);
524 static u32 optimize_vcore_voltage(struct volts const *v)
532 switch (v->efuse.reg_bits) {
534 val = readw(v->efuse.reg);
537 val = readl(v->efuse.reg);
540 printf("Error: efuse 0x%08x bits=%d unknown\n",
541 v->efuse.reg, v->efuse.reg_bits);
546 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
547 v->efuse.reg, v->efuse.reg_bits, v->value);
551 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
552 __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
557 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
558 * We set the maximum voltages allowed here because Smart-Reflex is not
559 * enabled in bootloader. Voltage initialization in the kernel will set
560 * these to the nominal values after enabling Smart-Reflex
562 void scale_vcores(struct vcores_data const *vcores)
566 val = optimize_vcore_voltage(&vcores->core);
567 do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
569 val = optimize_vcore_voltage(&vcores->mpu);
570 do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
572 /* Configure MPU ABB LDO after scale */
573 abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
574 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
575 (*prcm)->prm_abbldo_mpu_setup,
576 (*prcm)->prm_abbldo_mpu_ctrl,
577 (*prcm)->prm_irqstatus_mpu_2,
578 OMAP_ABB_MPU_TXDONE_MASK,
581 val = optimize_vcore_voltage(&vcores->mm);
582 do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
584 val = optimize_vcore_voltage(&vcores->gpu);
585 do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
587 val = optimize_vcore_voltage(&vcores->eve);
588 do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
590 val = optimize_vcore_voltage(&vcores->iva);
591 do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
593 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
594 /* Configure LDO SRAM "magic" bits */
595 writel(2, (*prcm)->prm_sldo_core_setup);
596 writel(2, (*prcm)->prm_sldo_mpu_setup);
597 writel(2, (*prcm)->prm_sldo_mm_setup);
601 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
603 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
604 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
605 debug("Enable clock domain - %x\n", clkctrl_reg);
608 static inline void wait_for_clk_enable(u32 clkctrl_addr)
610 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
613 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
614 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
616 clkctrl = readl(clkctrl_addr);
617 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
618 MODULE_CLKCTRL_IDLEST_SHIFT;
620 printf("Clock enable failed for 0x%x idlest 0x%x\n",
621 clkctrl_addr, clkctrl);
627 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
630 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
631 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
632 debug("Enable clock module - %x\n", clkctrl_addr);
634 wait_for_clk_enable(clkctrl_addr);
637 void freq_update_core(void)
639 u32 freq_config1 = 0;
640 const struct dpll_params *core_dpll_params;
641 u32 omap_rev = omap_revision();
643 core_dpll_params = get_core_dpll_params(*dplls_data);
644 /* Put EMIF clock domain in sw wakeup mode */
645 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
646 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
647 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
648 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
650 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
651 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
653 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
654 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
656 freq_config1 |= (core_dpll_params->m2 <<
657 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
658 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
660 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
661 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
662 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
663 puts("FREQ UPDATE procedure failed!!");
668 * Putting EMIF in HW_AUTO is seen to be causing issues with
669 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
670 * in OMAP5430 ES1.0 silicon
672 if (omap_rev != OMAP5430_ES1_0) {
673 /* Put EMIF clock domain back in hw auto mode */
674 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
675 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
676 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
677 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
681 void bypass_dpll(u32 const base)
683 do_bypass_dpll(base);
684 wait_for_bypass(base);
687 void lock_dpll(u32 const base)
693 void setup_clocks_for_console(void)
695 /* Do not add any spl_debug prints in this function */
696 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
697 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
698 CD_CLKCTRL_CLKTRCTRL_SHIFT);
700 /* Enable all UARTs - console will be on one of them */
701 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
702 MODULE_CLKCTRL_MODULEMODE_MASK,
703 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
704 MODULE_CLKCTRL_MODULEMODE_SHIFT);
706 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
707 MODULE_CLKCTRL_MODULEMODE_MASK,
708 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
709 MODULE_CLKCTRL_MODULEMODE_SHIFT);
711 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
712 MODULE_CLKCTRL_MODULEMODE_MASK,
713 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
714 MODULE_CLKCTRL_MODULEMODE_SHIFT);
716 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
717 MODULE_CLKCTRL_MODULEMODE_MASK,
718 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
719 MODULE_CLKCTRL_MODULEMODE_SHIFT);
721 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
722 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
723 CD_CLKCTRL_CLKTRCTRL_SHIFT);
726 void do_enable_clocks(u32 const *clk_domains,
727 u32 const *clk_modules_hw_auto,
728 u32 const *clk_modules_explicit_en,
733 /* Put the clock domains in SW_WKUP mode */
734 for (i = 0; (i < max) && clk_domains[i]; i++) {
735 enable_clock_domain(clk_domains[i],
736 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
739 /* Clock modules that need to be put in HW_AUTO */
740 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
741 enable_clock_module(clk_modules_hw_auto[i],
742 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
746 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
747 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
748 enable_clock_module(clk_modules_explicit_en[i],
749 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
753 /* Put the clock domains in HW_AUTO mode now */
754 for (i = 0; (i < max) && clk_domains[i]; i++) {
755 enable_clock_domain(clk_domains[i],
756 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
762 switch (omap_hw_init_context()) {
763 case OMAP_INIT_CONTEXT_SPL:
764 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
765 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
766 enable_basic_clocks();
768 scale_vcores(*omap_vcores);
770 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
771 setup_non_essential_dplls();
772 enable_non_essential_clocks();
774 setup_warmreset_time();
780 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
781 enable_basic_uboot_clocks();
784 void gpi2c_init(void)
786 static int gpi2c = 1;
789 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);