3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
41 #ifndef CONFIG_SPL_BUILD
43 * printing to console doesn't work unless
44 * this code is executed from SPL
46 #define printf(fmt, args...)
50 const u32 sys_clk_array[8] = {
51 12000000, /* 12 MHz */
52 13000000, /* 13 MHz */
53 16800000, /* 16.8 MHz */
54 19200000, /* 19.2 MHz */
55 26000000, /* 26 MHz */
56 27000000, /* 27 MHz */
57 38400000, /* 38.4 MHz */
58 20000000, /* 20 MHz */
61 static inline u32 __get_sys_clk_index(void)
65 * For ES1 the ROM code calibration of sys clock is not reliable
66 * due to hw issue. So, use hard-coded value. If this value is not
67 * correct for any board over-ride this function in board file
68 * From ES2.0 onwards you will get this information from
71 if (omap_revision() == OMAP4430_ES1_0)
72 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
74 /* SYS_CLKSEL - 1 to match the dpll param array indices */
75 ind = (readl((*prcm)->cm_sys_clksel) &
76 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
78 * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
79 * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
80 * NUM_SYS_CLK. So considering the last 3 bits as the index
81 * for the dpll param array.
83 ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
88 u32 get_sys_clk_index(void)
89 __attribute__ ((weak, alias("__get_sys_clk_index")));
91 u32 get_sys_clk_freq(void)
93 u8 index = get_sys_clk_index();
94 return sys_clk_array[index];
97 void setup_post_dividers(u32 const base, const struct dpll_params *params)
99 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
101 /* Setup post-dividers */
103 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
105 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
106 if (params->m4_h11 >= 0)
107 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
108 if (params->m5_h12 >= 0)
109 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
110 if (params->m6_h13 >= 0)
111 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
112 if (params->m7_h14 >= 0)
113 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
114 if (params->h21 >= 0)
115 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
116 if (params->h22 >= 0)
117 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
118 if (params->h23 >= 0)
119 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
120 if (params->h24 >= 0)
121 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
124 static inline void do_bypass_dpll(u32 const base)
126 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
128 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
129 CM_CLKMODE_DPLL_DPLL_EN_MASK,
130 DPLL_EN_FAST_RELOCK_BYPASS <<
131 CM_CLKMODE_DPLL_EN_SHIFT);
134 static inline void wait_for_bypass(u32 const base)
136 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
138 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
140 printf("Bypassing DPLL failed %x\n", base);
144 static inline void do_lock_dpll(u32 const base)
146 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
148 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
149 CM_CLKMODE_DPLL_DPLL_EN_MASK,
150 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
153 static inline void wait_for_lock(u32 const base)
155 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
157 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
158 &dpll_regs->cm_idlest_dpll, LDELAY)) {
159 printf("DPLL locking failed for %x\n", base);
164 inline u32 check_for_lock(u32 const base)
166 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
167 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
172 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
174 u32 sysclk_ind = get_sys_clk_index();
175 return &dpll_data->mpu[sysclk_ind];
178 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
180 u32 sysclk_ind = get_sys_clk_index();
181 return &dpll_data->core[sysclk_ind];
184 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
186 u32 sysclk_ind = get_sys_clk_index();
187 return &dpll_data->per[sysclk_ind];
190 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
192 u32 sysclk_ind = get_sys_clk_index();
193 return &dpll_data->iva[sysclk_ind];
196 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
198 u32 sysclk_ind = get_sys_clk_index();
199 return &dpll_data->usb[sysclk_ind];
202 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
204 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
205 u32 sysclk_ind = get_sys_clk_index();
206 return &dpll_data->abe[sysclk_ind];
208 return dpll_data->abe;
212 static const struct dpll_params *get_ddr_dpll_params
213 (struct dplls const *dpll_data)
215 u32 sysclk_ind = get_sys_clk_index();
219 return &dpll_data->ddr[sysclk_ind];
222 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
226 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
231 temp = readl(&dpll_regs->cm_clksel_dpll);
233 if (check_for_lock(base)) {
235 * The Dpll has already been locked by rom code using CH.
236 * Check if M,N are matching with Ideal nominal opp values.
237 * If matches, skip the rest otherwise relock.
239 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
240 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
241 if ((M != (params->m)) || (N != (params->n))) {
242 debug("\n %s Dpll locked, but not for ideal M = %d,"
243 "N = %d values, current values are M = %d,"
244 "N= %d" , dpll, params->m, params->n,
247 /* Dpll locked with ideal values for nominal opps. */
248 debug("\n %s Dpll already locked with ideal"
249 "nominal opp values", dpll);
250 goto setup_post_dividers;
257 temp &= ~CM_CLKSEL_DPLL_M_MASK;
258 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
260 temp &= ~CM_CLKSEL_DPLL_N_MASK;
261 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
263 writel(temp, &dpll_regs->cm_clksel_dpll);
270 setup_post_dividers(base, params);
272 /* Wait till the DPLL locks */
277 u32 omap_ddr_clk(void)
279 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
280 const struct dpll_params *core_dpll_params;
282 omap_rev = omap_revision();
283 sys_clk_khz = get_sys_clk_freq() / 1000;
285 core_dpll_params = get_core_dpll_params(*dplls_data);
287 debug("sys_clk %d\n ", sys_clk_khz * 1000);
289 /* Find Core DPLL locked frequency first */
290 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
291 (core_dpll_params->n + 1);
293 if (omap_rev < OMAP5430_ES1_0) {
295 * DDR frequency is PHY_ROOT_CLK/2
296 * PHY_ROOT_CLK = Fdpll/2/M2
301 * DDR frequency is PHY_ROOT_CLK
302 * PHY_ROOT_CLK = Fdpll/2/M2
307 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
308 ddr_clk *= 1000; /* convert to Hz */
309 debug("ddr_clk %d\n ", ddr_clk);
317 * Resulting MPU frequencies:
318 * 4430 ES1.0 : 600 MHz
319 * 4430 ES2.x : 792 MHz (OPP Turbo)
320 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
322 void configure_mpu_dpll(void)
324 const struct dpll_params *params;
325 struct dpll_regs *mpu_dpll_regs;
327 omap_rev = omap_revision();
330 * DCC and clock divider settings for 4460.
331 * DCC is required, if more than a certain frequency is required.
335 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
337 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
338 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
339 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
340 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
341 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
342 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
343 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
344 CM_CLKSEL_DCC_EN_MASK);
347 params = get_mpu_dpll_params(*dplls_data);
349 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
350 debug("MPU DPLL locked\n");
353 #ifdef CONFIG_USB_EHCI_OMAP
354 static void setup_usb_dpll(void)
356 const struct dpll_params *params;
357 u32 sys_clk_khz, sd_div, num, den;
359 sys_clk_khz = get_sys_clk_freq() / 1000;
362 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
363 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
364 * - where CLKINP is sys_clk in MHz
365 * Use CLKINP in KHz and adjust the denominator accordingly so
366 * that we have enough accuracy and at the same time no overflow
368 params = get_usb_dpll_params(*dplls_data);
369 num = params->m * sys_clk_khz;
370 den = (params->n + 1) * 250 * 1000;
373 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
374 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
375 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
377 /* Now setup the dpll with the regular function */
378 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
382 static void setup_dplls(void)
385 const struct dpll_params *params;
387 debug("setup_dplls\n");
390 params = get_core_dpll_params(*dplls_data); /* default - safest */
392 * Do not lock the core DPLL now. Just set it up.
393 * Core DPLL will be locked after setting up EMIF
394 * using the FREQ_UPDATE method(freq_update_core())
396 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
397 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
398 DPLL_NO_LOCK, "core");
400 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
402 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
403 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
404 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
405 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
406 writel(temp, (*prcm)->cm_clksel_core);
407 debug("Core DPLL configured\n");
410 params = get_per_dpll_params(*dplls_data);
411 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
412 params, DPLL_LOCK, "per");
413 debug("PER DPLL locked\n");
416 configure_mpu_dpll();
418 #ifdef CONFIG_USB_EHCI_OMAP
421 params = get_ddr_dpll_params(*dplls_data);
422 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
423 params, DPLL_LOCK, "ddr");
426 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
427 static void setup_non_essential_dplls(void)
430 const struct dpll_params *params;
433 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
434 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
436 params = get_iva_dpll_params(*dplls_data);
437 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
439 /* Configure ABE dpll */
440 params = get_abe_dpll_params(*dplls_data);
441 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
442 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
444 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
446 * We need to enable some additional options to achieve
447 * 196.608MHz from 32768 Hz
449 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
450 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
451 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
452 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
453 CM_CLKMODE_DPLL_REGM4XEN_MASK);
454 /* Spend 4 REFCLK cycles at each stage */
455 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
456 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
457 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
460 /* Select the right reference clk */
461 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
462 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
463 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
465 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
469 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
473 volt_offset -= pmic->base_offset;
475 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
478 * Offset codes 1-6 all give the base voltage in Palmas
479 * Offset code 0 switches OFF the SMPS
481 return offset_code + pmic->start_code;
484 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
487 u32 offset = volt_mv;
490 /* See if we can first get the GPIO if needed */
492 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
495 printf("%s: gpio %d request failed %d\n", __func__,
500 /* Pull the GPIO low to select SET0 register, while we program SET1 */
502 gpio_direction_output(pmic->gpio, 0);
504 /* convert to uV for better accuracy in the calculations */
507 offset_code = get_offset_code(offset, pmic);
509 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
512 if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
513 vcore_reg, offset_code))
514 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
517 gpio_direction_output(pmic->gpio, 1);
521 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
522 * We set the maximum voltages allowed here because Smart-Reflex is not
523 * enabled in bootloader. Voltage initialization in the kernel will set
524 * these to the nominal values after enabling Smart-Reflex
526 void scale_vcores(struct vcores_data const *vcores)
528 omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
530 do_scale_vcore(vcores->core.addr, vcores->core.value,
533 do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
536 do_scale_vcore(vcores->mm.addr, vcores->mm.value,
539 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
540 /* Configure LDO SRAM "magic" bits */
541 writel(2, (*prcm)->prm_sldo_core_setup);
542 writel(2, (*prcm)->prm_sldo_mpu_setup);
543 writel(2, (*prcm)->prm_sldo_mm_setup);
547 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
549 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
550 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
551 debug("Enable clock domain - %x\n", clkctrl_reg);
554 static inline void wait_for_clk_enable(u32 clkctrl_addr)
556 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
559 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
560 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
562 clkctrl = readl(clkctrl_addr);
563 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
564 MODULE_CLKCTRL_IDLEST_SHIFT;
566 printf("Clock enable failed for 0x%x idlest 0x%x\n",
567 clkctrl_addr, clkctrl);
573 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
576 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
577 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
578 debug("Enable clock module - %x\n", clkctrl_addr);
580 wait_for_clk_enable(clkctrl_addr);
583 void freq_update_core(void)
585 u32 freq_config1 = 0;
586 const struct dpll_params *core_dpll_params;
587 u32 omap_rev = omap_revision();
589 core_dpll_params = get_core_dpll_params(*dplls_data);
590 /* Put EMIF clock domain in sw wakeup mode */
591 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
592 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
593 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
594 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
596 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
597 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
599 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
600 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
602 freq_config1 |= (core_dpll_params->m2 <<
603 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
604 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
606 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
607 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
608 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
609 puts("FREQ UPDATE procedure failed!!");
614 * Putting EMIF in HW_AUTO is seen to be causing issues with
615 * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
616 * in OMAP5430 ES1.0 silicon
618 if (omap_rev != OMAP5430_ES1_0) {
619 /* Put EMIF clock domain back in hw auto mode */
620 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
621 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
622 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
623 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
627 void bypass_dpll(u32 const base)
629 do_bypass_dpll(base);
630 wait_for_bypass(base);
633 void lock_dpll(u32 const base)
639 void setup_clocks_for_console(void)
641 /* Do not add any spl_debug prints in this function */
642 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
643 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
644 CD_CLKCTRL_CLKTRCTRL_SHIFT);
646 /* Enable all UARTs - console will be on one of them */
647 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
648 MODULE_CLKCTRL_MODULEMODE_MASK,
649 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
650 MODULE_CLKCTRL_MODULEMODE_SHIFT);
652 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
653 MODULE_CLKCTRL_MODULEMODE_MASK,
654 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
655 MODULE_CLKCTRL_MODULEMODE_SHIFT);
657 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
658 MODULE_CLKCTRL_MODULEMODE_MASK,
659 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
660 MODULE_CLKCTRL_MODULEMODE_SHIFT);
662 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
663 MODULE_CLKCTRL_MODULEMODE_MASK,
664 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
665 MODULE_CLKCTRL_MODULEMODE_SHIFT);
667 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
668 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
669 CD_CLKCTRL_CLKTRCTRL_SHIFT);
672 void do_enable_clocks(u32 const *clk_domains,
673 u32 const *clk_modules_hw_auto,
674 u32 const *clk_modules_explicit_en,
679 /* Put the clock domains in SW_WKUP mode */
680 for (i = 0; (i < max) && clk_domains[i]; i++) {
681 enable_clock_domain(clk_domains[i],
682 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
685 /* Clock modules that need to be put in HW_AUTO */
686 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
687 enable_clock_module(clk_modules_hw_auto[i],
688 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
692 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
693 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
694 enable_clock_module(clk_modules_explicit_en[i],
695 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
699 /* Put the clock domains in HW_AUTO mode now */
700 for (i = 0; (i < max) && clk_domains[i]; i++) {
701 enable_clock_domain(clk_domains[i],
702 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
708 switch (omap_hw_init_context()) {
709 case OMAP_INIT_CONTEXT_SPL:
710 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
711 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
712 enable_basic_clocks();
713 scale_vcores(*omap_vcores);
715 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
716 setup_non_essential_dplls();
717 enable_non_essential_clocks();
724 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
725 enable_basic_uboot_clocks();