5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
35 inline u32 emif_num(u32 base)
37 if (base == EMIF1_BASE)
39 else if (base == EMIF2_BASE)
46 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
49 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
51 mr_addr |= cs << EMIF_REG_CS_SHIFT;
52 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
53 if (omap_revision() == OMAP4430_ES2_0)
54 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
56 mr = readl(&emif->emif_lpddr2_mode_reg_data);
57 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
62 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
64 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
66 mr_addr |= cs << EMIF_REG_CS_SHIFT;
67 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
68 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
71 void emif_reset_phy(u32 base)
73 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
76 iodft = readl(&emif->emif_iodft_tlgc);
77 iodft |= EMIF_REG_RESET_PHY_MASK;
78 writel(iodft, &emif->emif_iodft_tlgc);
81 static void do_lpddr2_init(u32 base, u32 cs)
85 /* Wait till device auto initialization is complete */
86 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
88 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
91 * Enough loops assuming a maximum of 2GHz
96 if (omap_revision() >= OMAP5430_ES1_0)
97 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
99 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
101 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
104 * Enable refresh along with writing MR2
105 * Encoding of RL in MR2 is (RL - 2)
107 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
108 set_mr(base, cs, mr_addr, RL_FINAL - 2);
110 if (omap_revision() >= OMAP5430_ES1_0)
111 set_mr(base, cs, LPDDR2_MR3, 0x1);
114 static void lpddr2_init(u32 base, const struct emif_regs *regs)
116 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
117 u32 *ext_phy_ctrl_base = 0;
118 u32 *emif_ext_phy_ctrl_base = 0;
122 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
125 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
126 * when EMIF_SDRAM_CONFIG register is written
128 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
131 * Set the SDRAM_CONFIG and PHY_CTRL for the
132 * un-locked frequency & default RL
134 writel(regs->sdram_config_init, &emif->emif_sdram_config);
135 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
137 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
138 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
140 if (omap_revision() >= OMAP5430_ES1_0) {
141 /* Configure external phy control timing registers */
142 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
143 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
144 /* Update shadow registers */
145 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
149 * external phy 6-24 registers do not change with
152 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
153 writel(ext_phy_ctrl_const_base[i],
154 emif_ext_phy_ctrl_base++);
155 /* Update shadow registers */
156 writel(ext_phy_ctrl_const_base[i],
157 emif_ext_phy_ctrl_base++);
161 do_lpddr2_init(base, CS0);
162 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
163 do_lpddr2_init(base, CS1);
165 writel(regs->sdram_config, &emif->emif_sdram_config);
166 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
168 /* Enable refresh now */
169 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
173 void emif_update_timings(u32 base, const struct emif_regs *regs)
175 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
177 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
178 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
179 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
180 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
181 if (omap_revision() == OMAP4430_ES1_0) {
182 /* ES1 bug EMIF should be in force idle during freq_update */
183 writel(0, &emif->emif_pwr_mgmt_ctrl);
185 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
186 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
188 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
189 writel(regs->zq_config, &emif->emif_zq_config);
190 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
191 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
193 if (omap_revision() == OMAP5430_ES1_0) {
194 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
195 &emif->emif_l3_config);
196 } else if (omap_revision() >= OMAP4460_ES1_0) {
197 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
198 &emif->emif_l3_config);
200 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
201 &emif->emif_l3_config);
205 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
206 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
209 * Organization and refresh requirements for LPDDR2 devices of different
210 * types and densities. Derived from JESD209-2 section 2.4
212 const struct lpddr2_addressing addressing_table[] = {
213 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
214 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
215 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
216 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
217 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
218 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
219 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
220 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
221 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
222 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
223 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
226 static const u32 lpddr2_density_2_size_in_mbytes[] = {
240 * Calculate the period of DDR clock from frequency value and set the
241 * denominator and numerator in global variables for easy access later
243 static void set_ddr_clk_period(u32 freq)
247 * period_in_ns = 10^9/freq
251 cancel_out(T_num, T_den, 200);
256 * Convert time in nano seconds to number of cycles of DDR clock
258 static inline u32 ns_2_cycles(u32 ns)
260 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
264 * ns_2_cycles with the difference that the time passed is 2 times the actual
265 * value(to avoid fractions). The cycles returned is for the original value of
266 * the timing parameter
268 static inline u32 ns_x2_2_cycles(u32 ns)
270 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
274 * Find addressing table index based on the device's type(S2 or S4) and
277 s8 addressing_table_index(u8 type, u8 density, u8 width)
280 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
284 * Look at the way ADDR_TABLE_INDEX* values have been defined
285 * in emif.h compared to LPDDR2_DENSITY_* values
286 * The table is layed out in the increasing order of density
287 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
290 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
291 index = ADDR_TABLE_INDEX1GS2;
292 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
293 index = ADDR_TABLE_INDEX2GS2;
297 debug("emif: addressing table index %d\n", index);
303 * Find the the right timing table from the array of timing
304 * tables of the device using DDR clock frequency
306 static const struct lpddr2_ac_timings *get_timings_table(const struct
307 lpddr2_ac_timings const *const *device_timings,
310 u32 i, temp, freq_nearest;
311 const struct lpddr2_ac_timings *timings = 0;
313 emif_assert(freq <= MAX_LPDDR2_FREQ);
314 emif_assert(device_timings);
317 * Start with the maximum allowed frequency - that is always safe
319 freq_nearest = MAX_LPDDR2_FREQ;
321 * Find the timings table that has the max frequency value:
322 * i. Above or equal to the DDR frequency - safe
323 * ii. The lowest that satisfies condition (i) - optimal
325 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
326 temp = device_timings[i]->max_freq;
327 if ((temp >= freq) && (temp <= freq_nearest)) {
329 timings = device_timings[i];
332 debug("emif: timings table: %d\n", freq_nearest);
337 * Finds the value of emif_sdram_config_reg
338 * All parameters are programmed based on the device on CS0.
339 * If there is a device on CS1, it will be same as that on CS0 or
340 * it will be NVM. We don't support NVM yet.
341 * If cs1_device pointer is NULL it is assumed that there is no device
344 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
345 const struct lpddr2_device_details *cs1_device,
346 const struct lpddr2_addressing *addressing,
351 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
352 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
353 EMIF_REG_IBANK_POS_SHIFT;
355 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
357 config_reg |= RL << EMIF_REG_CL_SHIFT;
359 config_reg |= addressing->row_sz[cs0_device->io_width] <<
360 EMIF_REG_ROWSIZE_SHIFT;
362 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
364 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
365 EMIF_REG_EBANK_SHIFT;
367 config_reg |= addressing->col_sz[cs0_device->io_width] <<
368 EMIF_REG_PAGESIZE_SHIFT;
373 static u32 get_sdram_ref_ctrl(u32 freq,
374 const struct lpddr2_addressing *addressing)
376 u32 ref_ctrl = 0, val = 0, freq_khz;
377 freq_khz = freq / 1000;
379 * refresh rate to be set is 'tREFI * freq in MHz
380 * division by 10000 to account for khz and x10 in t_REFI_us_x10
382 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
383 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
388 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
389 const struct lpddr2_min_tck *min_tck,
390 const struct lpddr2_addressing *addressing)
392 u32 tim1 = 0, val = 0;
393 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
394 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
396 if (addressing->num_banks == BANKS8)
397 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
400 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
402 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
404 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
405 tim1 |= val << EMIF_REG_T_RC_SHIFT;
407 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
408 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
410 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
411 tim1 |= val << EMIF_REG_T_WR_SHIFT;
413 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
414 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
416 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
417 tim1 |= val << EMIF_REG_T_RP_SHIFT;
422 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
423 const struct lpddr2_min_tck *min_tck)
425 u32 tim2 = 0, val = 0;
426 val = max(min_tck->tCKE, timings->tCKE) - 1;
427 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
429 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
430 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
433 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
436 val = ns_2_cycles(timings->tXSR) - 1;
437 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
438 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
440 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
441 tim2 |= val << EMIF_REG_T_XP_SHIFT;
446 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
447 const struct lpddr2_min_tck *min_tck,
448 const struct lpddr2_addressing *addressing)
450 u32 tim3 = 0, val = 0;
451 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
452 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
454 val = ns_2_cycles(timings->tRFCab) - 1;
455 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
457 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
458 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
460 val = ns_2_cycles(timings->tZQCS) - 1;
461 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
463 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
464 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
469 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
470 const struct lpddr2_addressing *addressing,
476 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
477 addressing->t_REFI_us_x10;
480 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
481 addressing->t_REFI_us_x10;
482 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
484 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
486 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
488 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
491 * Assuming that two chipselects have a single calibration resistor
492 * If there are indeed two calibration resistors, then this flag should
493 * be enabled to take advantage of dual calibration feature.
494 * This data should ideally come from board files. But considering
495 * that none of the boards today have calibration resistors per CS,
496 * it would be an unnecessary overhead.
498 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
500 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
502 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
507 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
508 const struct lpddr2_addressing *addressing,
511 u32 alert = 0, interval;
513 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
516 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
518 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
520 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
522 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
524 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
526 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
531 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
533 u32 idle = 0, val = 0;
535 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
537 /*Maximum value in normal conditions - suggested by hw team */
539 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
541 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
546 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
548 u32 phy = 0, val = 0;
550 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
552 if (freq <= 100000000)
553 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
554 else if (freq <= 200000000)
555 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
557 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
558 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
560 /* Other fields are constant magic values. Hardcode them together */
561 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
562 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
567 static u32 get_emif_mem_size(struct emif_device_details *devices)
569 u32 size_mbytes = 0, temp;
574 if (devices->cs0_device_details) {
575 temp = devices->cs0_device_details->density;
576 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
579 if (devices->cs1_device_details) {
580 temp = devices->cs1_device_details->density;
581 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
583 /* convert to bytes */
584 return size_mbytes << 20;
587 /* Gets the encoding corresponding to a given DMM section size */
588 u32 get_dmm_section_size_map(u32 section_size)
591 * Section size mapping:
592 * 0x0: 16-MiB section
593 * 0x1: 32-MiB section
594 * 0x2: 64-MiB section
595 * 0x3: 128-MiB section
596 * 0x4: 256-MiB section
597 * 0x5: 512-MiB section
601 section_size >>= 24; /* divide by 16 MB */
602 return log_2_n_round_down(section_size);
605 static void emif_calculate_regs(
606 const struct emif_device_details *emif_dev_details,
607 u32 freq, struct emif_regs *regs)
610 const struct lpddr2_addressing *addressing;
611 const struct lpddr2_ac_timings *timings;
612 const struct lpddr2_min_tck *min_tck;
613 const struct lpddr2_device_details *cs0_dev_details =
614 emif_dev_details->cs0_device_details;
615 const struct lpddr2_device_details *cs1_dev_details =
616 emif_dev_details->cs1_device_details;
617 const struct lpddr2_device_timings *cs0_dev_timings =
618 emif_dev_details->cs0_device_timings;
620 emif_assert(emif_dev_details);
623 * You can not have a device on CS1 without one on CS0
624 * So configuring EMIF without a device on CS0 doesn't
627 emif_assert(cs0_dev_details);
628 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
630 * If there is a device on CS1 it should be same type as CS0
631 * (or NVM. But NVM is not supported in this driver yet)
633 emif_assert((cs1_dev_details == NULL) ||
634 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
635 (cs0_dev_details->type == cs1_dev_details->type));
636 emif_assert(freq <= MAX_LPDDR2_FREQ);
638 set_ddr_clk_period(freq);
641 * The device on CS0 is used for all timing calculations
642 * There is only one set of registers for timings per EMIF. So, if the
643 * second CS(CS1) has a device, it should have the same timings as the
646 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
647 emif_assert(timings);
648 min_tck = cs0_dev_timings->min_tck;
650 temp = addressing_table_index(cs0_dev_details->type,
651 cs0_dev_details->density,
652 cs0_dev_details->io_width);
654 emif_assert((temp >= 0));
655 addressing = &(addressing_table[temp]);
656 emif_assert(addressing);
658 sys_freq = get_sys_clk_freq();
660 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
662 addressing, RL_BOOT);
664 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
666 addressing, RL_FINAL);
668 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
670 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
672 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
674 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
676 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
678 regs->temp_alert_config =
679 get_temp_alert_config(cs1_dev_details, addressing, 0);
681 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
682 LPDDR2_VOLTAGE_STABLE);
684 regs->emif_ddr_phy_ctlr_1_init =
685 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
687 regs->emif_ddr_phy_ctlr_1 =
688 get_ddr_phy_ctrl_1(freq, RL_FINAL);
692 print_timing_reg(regs->sdram_config_init);
693 print_timing_reg(regs->sdram_config);
694 print_timing_reg(regs->ref_ctrl);
695 print_timing_reg(regs->sdram_tim1);
696 print_timing_reg(regs->sdram_tim2);
697 print_timing_reg(regs->sdram_tim3);
698 print_timing_reg(regs->read_idle_ctrl);
699 print_timing_reg(regs->temp_alert_config);
700 print_timing_reg(regs->zq_config);
701 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
702 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
704 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
706 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
707 const char *get_lpddr2_type(u8 type_id)
719 const char *get_lpddr2_io_width(u8 width_id)
722 case LPDDR2_IO_WIDTH_8:
724 case LPDDR2_IO_WIDTH_16:
726 case LPDDR2_IO_WIDTH_32:
733 const char *get_lpddr2_manufacturer(u32 manufacturer)
735 switch (manufacturer) {
736 case LPDDR2_MANUFACTURER_SAMSUNG:
738 case LPDDR2_MANUFACTURER_QIMONDA:
740 case LPDDR2_MANUFACTURER_ELPIDA:
742 case LPDDR2_MANUFACTURER_ETRON:
744 case LPDDR2_MANUFACTURER_NANYA:
746 case LPDDR2_MANUFACTURER_HYNIX:
748 case LPDDR2_MANUFACTURER_MOSEL:
750 case LPDDR2_MANUFACTURER_WINBOND:
752 case LPDDR2_MANUFACTURER_ESMT:
754 case LPDDR2_MANUFACTURER_SPANSION:
756 case LPDDR2_MANUFACTURER_SST:
758 case LPDDR2_MANUFACTURER_ZMOS:
760 case LPDDR2_MANUFACTURER_INTEL:
762 case LPDDR2_MANUFACTURER_NUMONYX:
764 case LPDDR2_MANUFACTURER_MICRON:
771 static void display_sdram_details(u32 emif_nr, u32 cs,
772 struct lpddr2_device_details *device)
775 const char *type_str;
776 char density_str[10];
779 debug("EMIF%d CS%d\t", emif_nr, cs);
786 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
787 type_str = get_lpddr2_type(device->type);
789 density = lpddr2_density_2_size_in_mbytes[device->density];
790 if ((density / 1024 * 1024) == density) {
792 sprintf(density_str, "%d GB", density);
794 sprintf(density_str, "%d MB", density);
795 if (mfg_str && type_str)
796 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
799 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
800 struct lpddr2_device_details *lpddr2_device)
804 mr = get_mr(base, cs, LPDDR2_MR0);
806 /* Mode register value bigger than 8 bit */
810 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
815 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
818 /* DNV supported - But DNV is only supported for NVM */
822 mr = get_mr(base, cs, LPDDR2_MR4);
824 /* Mode register value bigger than 8 bit */
828 mr = get_mr(base, cs, LPDDR2_MR5);
830 /* Mode register value bigger than 8 bit */
834 if (!get_lpddr2_manufacturer(mr)) {
835 /* Manufacturer not identified */
838 lpddr2_device->manufacturer = mr;
840 mr = get_mr(base, cs, LPDDR2_MR6);
842 /* Mode register value bigger than 8 bit */
846 mr = get_mr(base, cs, LPDDR2_MR7);
848 /* Mode register value bigger than 8 bit */
852 mr = get_mr(base, cs, LPDDR2_MR8);
854 /* Mode register value bigger than 8 bit */
858 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
859 if (!get_lpddr2_type(temp)) {
863 lpddr2_device->type = temp;
865 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
866 if (temp > LPDDR2_DENSITY_32Gb) {
867 /* Density not supported */
870 lpddr2_device->density = temp;
872 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
873 if (!get_lpddr2_io_width(temp)) {
874 /* IO width unsupported value */
877 lpddr2_device->io_width = temp;
880 * If all the above tests pass we should
881 * have a device on this chip-select
886 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
887 struct lpddr2_device_details *lpddr2_dev_details)
890 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
892 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
894 if (!lpddr2_dev_details)
897 /* Do the minimum init for mode register accesses */
898 if (!running_from_sdram()) {
899 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
900 writel(phy, &emif->emif_ddr_phy_ctrl_1);
903 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
906 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
908 return lpddr2_dev_details;
910 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
912 static void do_sdram_init(u32 base)
914 const struct emif_regs *regs;
915 u32 in_sdram, emif_nr;
917 debug(">>do_sdram_init() %x\n", base);
919 in_sdram = running_from_sdram();
920 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
922 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
923 emif_get_reg_dump(emif_nr, ®s);
925 debug("EMIF: reg dump not provided\n");
930 * The user has not provided the register values. We need to
931 * calculate it based on the timings and the DDR frequency
933 struct emif_device_details dev_details;
934 struct emif_regs calculated_regs;
937 * Get device details:
938 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
939 * - Obtained from user otherwise
941 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
942 emif_reset_phy(base);
943 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
945 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
947 emif_reset_phy(base);
949 /* Return if no devices on this EMIF */
950 if (!dev_details.cs0_device_details &&
951 !dev_details.cs1_device_details) {
952 emif_sizes[emif_nr - 1] = 0;
957 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
960 * Get device timings:
961 * - Default timings specified by JESD209-2 if
962 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
963 * - Obtained from user otherwise
965 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
966 &dev_details.cs1_device_timings);
968 /* Calculate the register values */
969 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
970 regs = &calculated_regs;
971 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
974 * Initializing the LPDDR2 device can not happen from SDRAM.
975 * Changing the timing registers in EMIF can happen(going from one
979 lpddr2_init(base, regs);
981 /* Write to the shadow registers */
982 emif_update_timings(base, regs);
984 debug("<<do_sdram_init() %x\n", base);
987 void emif_post_init_config(u32 base)
989 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
990 u32 omap_rev = omap_revision();
992 if (omap_rev == OMAP5430_ES1_0)
995 /* reset phy on ES2.0 */
996 if (omap_rev == OMAP4430_ES2_0)
997 emif_reset_phy(base);
999 /* Put EMIF back in smart idle on ES1.0 */
1000 if (omap_rev == OMAP4430_ES1_0)
1001 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1004 void dmm_init(u32 base)
1006 const struct dmm_lisa_map_regs *lisa_map_regs;
1008 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1009 emif_get_dmm_regs(&lisa_map_regs);
1011 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1012 u32 section_cnt, sys_addr;
1013 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1017 sys_addr = CONFIG_SYS_SDRAM_BASE;
1018 emif1_size = emif_sizes[0];
1019 emif2_size = emif_sizes[1];
1020 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1022 if (!emif1_size && !emif2_size)
1025 /* symmetric interleaved section */
1026 if (emif1_size && emif2_size) {
1027 mapped_size = min(emif1_size, emif2_size);
1028 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1029 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1031 section_map |= (sys_addr >> 24) <<
1032 EMIF_SYS_ADDR_SHIFT;
1033 section_map |= get_dmm_section_size_map(mapped_size * 2)
1034 << EMIF_SYS_SIZE_SHIFT;
1035 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1036 emif1_size -= mapped_size;
1037 emif2_size -= mapped_size;
1038 sys_addr += (mapped_size * 2);
1043 * Single EMIF section(we can have a maximum of 1 single EMIF
1044 * section- either EMIF1 or EMIF2 or none, but not both)
1047 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1048 section_map |= get_dmm_section_size_map(emif1_size)
1049 << EMIF_SYS_SIZE_SHIFT;
1051 section_map |= (mapped_size >> 24) <<
1052 EMIF_SDRC_ADDR_SHIFT;
1054 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1058 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1059 section_map |= get_dmm_section_size_map(emif2_size) <<
1060 EMIF_SYS_SIZE_SHIFT;
1062 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1064 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1068 if (section_cnt == 2) {
1069 /* Only 1 section - either symmetric or single EMIF */
1070 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1071 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1072 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1074 /* 2 sections - 1 symmetric, 1 single EMIF */
1075 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1076 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1079 /* TRAP for invalid TILER mappings in section 0 */
1080 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1082 lisa_map_regs = &lis_map_regs_calculated;
1084 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1085 (struct dmm_lisa_map_regs *)base;
1087 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1088 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1089 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1090 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1092 writel(lisa_map_regs->dmm_lisa_map_3,
1093 &hw_lisa_map_regs->dmm_lisa_map_3);
1094 writel(lisa_map_regs->dmm_lisa_map_2,
1095 &hw_lisa_map_regs->dmm_lisa_map_2);
1096 writel(lisa_map_regs->dmm_lisa_map_1,
1097 &hw_lisa_map_regs->dmm_lisa_map_1);
1098 writel(lisa_map_regs->dmm_lisa_map_0,
1099 &hw_lisa_map_regs->dmm_lisa_map_0);
1101 if (omap_revision() >= OMAP4460_ES1_0) {
1103 (struct dmm_lisa_map_regs *)MA_BASE;
1105 writel(lisa_map_regs->dmm_lisa_map_3,
1106 &hw_lisa_map_regs->dmm_lisa_map_3);
1107 writel(lisa_map_regs->dmm_lisa_map_2,
1108 &hw_lisa_map_regs->dmm_lisa_map_2);
1109 writel(lisa_map_regs->dmm_lisa_map_1,
1110 &hw_lisa_map_regs->dmm_lisa_map_1);
1111 writel(lisa_map_regs->dmm_lisa_map_0,
1112 &hw_lisa_map_regs->dmm_lisa_map_0);
1117 * SDRAM initialization:
1118 * SDRAM initialization has two parts:
1119 * 1. Configuring the SDRAM device
1120 * 2. Update the AC timings related parameters in the EMIF module
1121 * (1) should be done only once and should not be done while we are
1122 * running from SDRAM.
1123 * (2) can and should be done more than once if OPP changes.
1124 * Particularly, this may be needed when we boot without SPL and
1125 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1126 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1127 * the frequency. So,
1128 * Doing (1) and (2) makes sense - first time initialization
1129 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1130 * Doing (1) and not (2) doen't make sense
1131 * See do_sdram_init() for the details
1133 void sdram_init(void)
1135 u32 in_sdram, size_prog, size_detect;
1137 debug(">>sdram_init()\n");
1139 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1142 in_sdram = running_from_sdram();
1143 debug("in_sdram = %d\n", in_sdram);
1146 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1149 do_sdram_init(EMIF1_BASE);
1150 do_sdram_init(EMIF2_BASE);
1154 emif_post_init_config(EMIF1_BASE);
1155 emif_post_init_config(EMIF2_BASE);
1158 /* for the shadow registers to take effect */
1161 /* Do some testing after the init */
1163 size_prog = omap_sdram_size();
1164 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1166 /* Compare with the size programmed */
1167 if (size_detect != size_prog) {
1168 printf("SDRAM: identified size not same as expected"
1169 " size identified: %x expected: %x\n",
1173 debug("get_ram_size() successful");
1176 debug("<<sdram_init()\n");