5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/omap_common.h>
17 #include <asm/utils.h>
18 #include <linux/compiler.h>
20 static int emif1_enabled = -1, emif2_enabled = -1;
22 void set_lpmode_selfrefresh(u32 base)
24 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
27 reg = readl(&emif->emif_pwr_mgmt_ctrl);
28 reg &= ~EMIF_REG_LP_MODE_MASK;
29 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
30 reg &= ~EMIF_REG_SR_TIM_MASK;
31 writel(reg, &emif->emif_pwr_mgmt_ctrl);
33 /* dummy read for the new SR_TIM to be loaded */
34 readl(&emif->emif_pwr_mgmt_ctrl);
37 void force_emif_self_refresh()
39 set_lpmode_selfrefresh(EMIF1_BASE);
40 set_lpmode_selfrefresh(EMIF2_BASE);
43 inline u32 emif_num(u32 base)
45 if (base == EMIF1_BASE)
47 else if (base == EMIF2_BASE)
54 * Get SDRAM type connected to EMIF.
55 * Assuming similar SDRAM parts are connected to both EMIF's
56 * which is typically the case. So it is sufficient to get
57 * SDRAM type from EMIF1.
61 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
63 return (readl(&emif->emif_sdram_config) &
64 EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
67 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
70 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
72 mr_addr |= cs << EMIF_REG_CS_SHIFT;
73 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
74 if (omap_revision() == OMAP4430_ES2_0)
75 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
77 mr = readl(&emif->emif_lpddr2_mode_reg_data);
78 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
80 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
81 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
82 ((mr & 0xff000000) >> 24) == (mr & 0xff))
88 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
90 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
92 mr_addr |= cs << EMIF_REG_CS_SHIFT;
93 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
94 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
97 void emif_reset_phy(u32 base)
99 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
102 iodft = readl(&emif->emif_iodft_tlgc);
103 iodft |= EMIF_REG_RESET_PHY_MASK;
104 writel(iodft, &emif->emif_iodft_tlgc);
107 static void do_lpddr2_init(u32 base, u32 cs)
110 const struct lpddr2_mr_regs *mr_regs;
112 get_lpddr2_mr_regs(&mr_regs);
113 /* Wait till device auto initialization is complete */
114 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
116 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
119 * Enough loops assuming a maximum of 2GHz
124 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
125 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
128 * Enable refresh along with writing MR2
129 * Encoding of RL in MR2 is (RL - 2)
131 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
132 set_mr(base, cs, mr_addr, mr_regs->mr2);
134 if (mr_regs->mr3 > 0)
135 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
138 static void lpddr2_init(u32 base, const struct emif_regs *regs)
140 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
143 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
146 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
147 * when EMIF_SDRAM_CONFIG register is written
149 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
152 * Set the SDRAM_CONFIG and PHY_CTRL for the
153 * un-locked frequency & default RL
155 writel(regs->sdram_config_init, &emif->emif_sdram_config);
156 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
158 do_ext_phy_settings(base, regs);
160 do_lpddr2_init(base, CS0);
161 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
162 do_lpddr2_init(base, CS1);
164 writel(regs->sdram_config, &emif->emif_sdram_config);
165 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
167 /* Enable refresh now */
168 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
172 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
176 void emif_update_timings(u32 base, const struct emif_regs *regs)
178 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
180 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
181 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
182 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
183 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
184 if (omap_revision() == OMAP4430_ES1_0) {
185 /* ES1 bug EMIF should be in force idle during freq_update */
186 writel(0, &emif->emif_pwr_mgmt_ctrl);
188 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
189 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
191 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
192 writel(regs->zq_config, &emif->emif_zq_config);
193 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
194 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
196 if ((omap_revision() >= OMAP5430_ES1_0) ||
197 (omap_revision() == DRA752_ES1_0)) {
198 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
199 &emif->emif_l3_config);
200 } else if (omap_revision() >= OMAP4460_ES1_0) {
201 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
202 &emif->emif_l3_config);
204 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
205 &emif->emif_l3_config);
209 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
211 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
213 /* keep sdram in self-refresh */
214 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
215 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
219 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
220 * Invert clock adds an additional half cycle delay on the command
221 * interface. The additional half cycle, is usually meant to enable
222 * leveling in the situation that DQS is later than CK on the board.It
223 * also helps provide some additional margin for leveling.
225 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
226 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
229 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
230 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
232 /* Launch Full leveling */
233 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
235 /* Wait till full leveling is complete */
236 readl(&emif->emif_rd_wr_lvl_ctl);
239 /* Read data eye leveling no of samples */
240 config_data_eye_leveling_samples(base);
242 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
243 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
246 /* Launch Incremental leveling */
247 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
251 static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
253 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
255 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
256 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
257 config_data_eye_leveling_samples(base);
259 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
260 writel(regs->sdram_config, &emif->emif_sdram_config);
263 static void ddr3_init(u32 base, const struct emif_regs *regs)
265 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
268 * Set SDRAM_CONFIG and PHY control registers to locked frequency
269 * and RL =7. As the default values of the Mode Registers are not
270 * defined, contents of mode Registers must be fully initialized.
271 * H/W takes care of this initialization
273 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
274 writel(regs->sdram_config_init, &emif->emif_sdram_config);
276 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
278 /* Update timing registers */
279 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
280 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
281 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
283 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
284 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
286 do_ext_phy_settings(base, regs);
288 /* enable leveling */
289 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
291 if (omap_revision() == DRA752_ES1_0)
292 ddr3_sw_leveling(base, regs);
294 ddr3_leveling(base, regs);
297 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
298 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
301 * Organization and refresh requirements for LPDDR2 devices of different
302 * types and densities. Derived from JESD209-2 section 2.4
304 const struct lpddr2_addressing addressing_table[] = {
305 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
306 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
307 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
308 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
309 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
310 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
311 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
312 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
313 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
314 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
315 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
318 static const u32 lpddr2_density_2_size_in_mbytes[] = {
332 * Calculate the period of DDR clock from frequency value and set the
333 * denominator and numerator in global variables for easy access later
335 static void set_ddr_clk_period(u32 freq)
339 * period_in_ns = 10^9/freq
343 cancel_out(T_num, T_den, 200);
348 * Convert time in nano seconds to number of cycles of DDR clock
350 static inline u32 ns_2_cycles(u32 ns)
352 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
356 * ns_2_cycles with the difference that the time passed is 2 times the actual
357 * value(to avoid fractions). The cycles returned is for the original value of
358 * the timing parameter
360 static inline u32 ns_x2_2_cycles(u32 ns)
362 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
366 * Find addressing table index based on the device's type(S2 or S4) and
369 s8 addressing_table_index(u8 type, u8 density, u8 width)
372 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
376 * Look at the way ADDR_TABLE_INDEX* values have been defined
377 * in emif.h compared to LPDDR2_DENSITY_* values
378 * The table is layed out in the increasing order of density
379 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
382 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
383 index = ADDR_TABLE_INDEX1GS2;
384 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
385 index = ADDR_TABLE_INDEX2GS2;
389 debug("emif: addressing table index %d\n", index);
395 * Find the the right timing table from the array of timing
396 * tables of the device using DDR clock frequency
398 static const struct lpddr2_ac_timings *get_timings_table(const struct
399 lpddr2_ac_timings const *const *device_timings,
402 u32 i, temp, freq_nearest;
403 const struct lpddr2_ac_timings *timings = 0;
405 emif_assert(freq <= MAX_LPDDR2_FREQ);
406 emif_assert(device_timings);
409 * Start with the maximum allowed frequency - that is always safe
411 freq_nearest = MAX_LPDDR2_FREQ;
413 * Find the timings table that has the max frequency value:
414 * i. Above or equal to the DDR frequency - safe
415 * ii. The lowest that satisfies condition (i) - optimal
417 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
418 temp = device_timings[i]->max_freq;
419 if ((temp >= freq) && (temp <= freq_nearest)) {
421 timings = device_timings[i];
424 debug("emif: timings table: %d\n", freq_nearest);
429 * Finds the value of emif_sdram_config_reg
430 * All parameters are programmed based on the device on CS0.
431 * If there is a device on CS1, it will be same as that on CS0 or
432 * it will be NVM. We don't support NVM yet.
433 * If cs1_device pointer is NULL it is assumed that there is no device
436 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
437 const struct lpddr2_device_details *cs1_device,
438 const struct lpddr2_addressing *addressing,
443 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
444 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
445 EMIF_REG_IBANK_POS_SHIFT;
447 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
449 config_reg |= RL << EMIF_REG_CL_SHIFT;
451 config_reg |= addressing->row_sz[cs0_device->io_width] <<
452 EMIF_REG_ROWSIZE_SHIFT;
454 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
456 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
457 EMIF_REG_EBANK_SHIFT;
459 config_reg |= addressing->col_sz[cs0_device->io_width] <<
460 EMIF_REG_PAGESIZE_SHIFT;
465 static u32 get_sdram_ref_ctrl(u32 freq,
466 const struct lpddr2_addressing *addressing)
468 u32 ref_ctrl = 0, val = 0, freq_khz;
469 freq_khz = freq / 1000;
471 * refresh rate to be set is 'tREFI * freq in MHz
472 * division by 10000 to account for khz and x10 in t_REFI_us_x10
474 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
475 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
480 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
481 const struct lpddr2_min_tck *min_tck,
482 const struct lpddr2_addressing *addressing)
484 u32 tim1 = 0, val = 0;
485 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
486 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
488 if (addressing->num_banks == BANKS8)
489 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
492 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
494 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
496 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
497 tim1 |= val << EMIF_REG_T_RC_SHIFT;
499 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
500 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
502 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
503 tim1 |= val << EMIF_REG_T_WR_SHIFT;
505 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
506 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
508 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
509 tim1 |= val << EMIF_REG_T_RP_SHIFT;
514 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
515 const struct lpddr2_min_tck *min_tck)
517 u32 tim2 = 0, val = 0;
518 val = max(min_tck->tCKE, timings->tCKE) - 1;
519 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
521 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
522 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
525 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
528 val = ns_2_cycles(timings->tXSR) - 1;
529 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
530 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
532 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
533 tim2 |= val << EMIF_REG_T_XP_SHIFT;
538 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
539 const struct lpddr2_min_tck *min_tck,
540 const struct lpddr2_addressing *addressing)
542 u32 tim3 = 0, val = 0;
543 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
544 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
546 val = ns_2_cycles(timings->tRFCab) - 1;
547 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
549 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
550 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
552 val = ns_2_cycles(timings->tZQCS) - 1;
553 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
555 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
556 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
561 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
562 const struct lpddr2_addressing *addressing,
568 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
569 addressing->t_REFI_us_x10;
572 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
573 addressing->t_REFI_us_x10;
574 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
576 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
578 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
580 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
583 * Assuming that two chipselects have a single calibration resistor
584 * If there are indeed two calibration resistors, then this flag should
585 * be enabled to take advantage of dual calibration feature.
586 * This data should ideally come from board files. But considering
587 * that none of the boards today have calibration resistors per CS,
588 * it would be an unnecessary overhead.
590 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
592 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
594 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
599 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
600 const struct lpddr2_addressing *addressing,
603 u32 alert = 0, interval;
605 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
608 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
610 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
612 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
614 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
616 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
618 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
623 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
625 u32 idle = 0, val = 0;
627 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
629 /*Maximum value in normal conditions - suggested by hw team */
631 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
633 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
638 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
640 u32 phy = 0, val = 0;
642 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
644 if (freq <= 100000000)
645 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
646 else if (freq <= 200000000)
647 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
649 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
650 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
652 /* Other fields are constant magic values. Hardcode them together */
653 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
654 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
659 static u32 get_emif_mem_size(u32 base)
661 u32 size_mbytes = 0, temp;
662 struct emif_device_details dev_details;
663 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
664 u32 emif_nr = emif_num(base);
666 emif_reset_phy(base);
667 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
669 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
671 emif_reset_phy(base);
673 if (dev_details.cs0_device_details) {
674 temp = dev_details.cs0_device_details->density;
675 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
678 if (dev_details.cs1_device_details) {
679 temp = dev_details.cs1_device_details->density;
680 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
682 /* convert to bytes */
683 return size_mbytes << 20;
686 /* Gets the encoding corresponding to a given DMM section size */
687 u32 get_dmm_section_size_map(u32 section_size)
690 * Section size mapping:
691 * 0x0: 16-MiB section
692 * 0x1: 32-MiB section
693 * 0x2: 64-MiB section
694 * 0x3: 128-MiB section
695 * 0x4: 256-MiB section
696 * 0x5: 512-MiB section
700 section_size >>= 24; /* divide by 16 MB */
701 return log_2_n_round_down(section_size);
704 static void emif_calculate_regs(
705 const struct emif_device_details *emif_dev_details,
706 u32 freq, struct emif_regs *regs)
709 const struct lpddr2_addressing *addressing;
710 const struct lpddr2_ac_timings *timings;
711 const struct lpddr2_min_tck *min_tck;
712 const struct lpddr2_device_details *cs0_dev_details =
713 emif_dev_details->cs0_device_details;
714 const struct lpddr2_device_details *cs1_dev_details =
715 emif_dev_details->cs1_device_details;
716 const struct lpddr2_device_timings *cs0_dev_timings =
717 emif_dev_details->cs0_device_timings;
719 emif_assert(emif_dev_details);
722 * You can not have a device on CS1 without one on CS0
723 * So configuring EMIF without a device on CS0 doesn't
726 emif_assert(cs0_dev_details);
727 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
729 * If there is a device on CS1 it should be same type as CS0
730 * (or NVM. But NVM is not supported in this driver yet)
732 emif_assert((cs1_dev_details == NULL) ||
733 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
734 (cs0_dev_details->type == cs1_dev_details->type));
735 emif_assert(freq <= MAX_LPDDR2_FREQ);
737 set_ddr_clk_period(freq);
740 * The device on CS0 is used for all timing calculations
741 * There is only one set of registers for timings per EMIF. So, if the
742 * second CS(CS1) has a device, it should have the same timings as the
745 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
746 emif_assert(timings);
747 min_tck = cs0_dev_timings->min_tck;
749 temp = addressing_table_index(cs0_dev_details->type,
750 cs0_dev_details->density,
751 cs0_dev_details->io_width);
753 emif_assert((temp >= 0));
754 addressing = &(addressing_table[temp]);
755 emif_assert(addressing);
757 sys_freq = get_sys_clk_freq();
759 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
761 addressing, RL_BOOT);
763 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
765 addressing, RL_FINAL);
767 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
769 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
771 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
773 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
775 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
777 regs->temp_alert_config =
778 get_temp_alert_config(cs1_dev_details, addressing, 0);
780 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
781 LPDDR2_VOLTAGE_STABLE);
783 regs->emif_ddr_phy_ctlr_1_init =
784 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
786 regs->emif_ddr_phy_ctlr_1 =
787 get_ddr_phy_ctrl_1(freq, RL_FINAL);
791 print_timing_reg(regs->sdram_config_init);
792 print_timing_reg(regs->sdram_config);
793 print_timing_reg(regs->ref_ctrl);
794 print_timing_reg(regs->sdram_tim1);
795 print_timing_reg(regs->sdram_tim2);
796 print_timing_reg(regs->sdram_tim3);
797 print_timing_reg(regs->read_idle_ctrl);
798 print_timing_reg(regs->temp_alert_config);
799 print_timing_reg(regs->zq_config);
800 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
801 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
803 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
805 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
806 const char *get_lpddr2_type(u8 type_id)
818 const char *get_lpddr2_io_width(u8 width_id)
821 case LPDDR2_IO_WIDTH_8:
823 case LPDDR2_IO_WIDTH_16:
825 case LPDDR2_IO_WIDTH_32:
832 const char *get_lpddr2_manufacturer(u32 manufacturer)
834 switch (manufacturer) {
835 case LPDDR2_MANUFACTURER_SAMSUNG:
837 case LPDDR2_MANUFACTURER_QIMONDA:
839 case LPDDR2_MANUFACTURER_ELPIDA:
841 case LPDDR2_MANUFACTURER_ETRON:
843 case LPDDR2_MANUFACTURER_NANYA:
845 case LPDDR2_MANUFACTURER_HYNIX:
847 case LPDDR2_MANUFACTURER_MOSEL:
849 case LPDDR2_MANUFACTURER_WINBOND:
851 case LPDDR2_MANUFACTURER_ESMT:
853 case LPDDR2_MANUFACTURER_SPANSION:
855 case LPDDR2_MANUFACTURER_SST:
857 case LPDDR2_MANUFACTURER_ZMOS:
859 case LPDDR2_MANUFACTURER_INTEL:
861 case LPDDR2_MANUFACTURER_NUMONYX:
863 case LPDDR2_MANUFACTURER_MICRON:
870 static void display_sdram_details(u32 emif_nr, u32 cs,
871 struct lpddr2_device_details *device)
874 const char *type_str;
875 char density_str[10];
878 debug("EMIF%d CS%d\t", emif_nr, cs);
885 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
886 type_str = get_lpddr2_type(device->type);
888 density = lpddr2_density_2_size_in_mbytes[device->density];
889 if ((density / 1024 * 1024) == density) {
891 sprintf(density_str, "%d GB", density);
893 sprintf(density_str, "%d MB", density);
894 if (mfg_str && type_str)
895 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
898 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
899 struct lpddr2_device_details *lpddr2_device)
903 mr = get_mr(base, cs, LPDDR2_MR0);
905 /* Mode register value bigger than 8 bit */
909 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
914 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
917 /* DNV supported - But DNV is only supported for NVM */
921 mr = get_mr(base, cs, LPDDR2_MR4);
923 /* Mode register value bigger than 8 bit */
927 mr = get_mr(base, cs, LPDDR2_MR5);
929 /* Mode register value bigger than 8 bit */
933 if (!get_lpddr2_manufacturer(mr)) {
934 /* Manufacturer not identified */
937 lpddr2_device->manufacturer = mr;
939 mr = get_mr(base, cs, LPDDR2_MR6);
941 /* Mode register value bigger than 8 bit */
945 mr = get_mr(base, cs, LPDDR2_MR7);
947 /* Mode register value bigger than 8 bit */
951 mr = get_mr(base, cs, LPDDR2_MR8);
953 /* Mode register value bigger than 8 bit */
957 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
958 if (!get_lpddr2_type(temp)) {
962 lpddr2_device->type = temp;
964 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
965 if (temp > LPDDR2_DENSITY_32Gb) {
966 /* Density not supported */
969 lpddr2_device->density = temp;
971 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
972 if (!get_lpddr2_io_width(temp)) {
973 /* IO width unsupported value */
976 lpddr2_device->io_width = temp;
979 * If all the above tests pass we should
980 * have a device on this chip-select
985 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
986 struct lpddr2_device_details *lpddr2_dev_details)
989 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
991 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
993 if (!lpddr2_dev_details)
996 /* Do the minimum init for mode register accesses */
997 if (!(running_from_sdram() || warm_reset())) {
998 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
999 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1002 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1005 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1007 return lpddr2_dev_details;
1009 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1011 static void do_sdram_init(u32 base)
1013 const struct emif_regs *regs;
1014 u32 in_sdram, emif_nr;
1016 debug(">>do_sdram_init() %x\n", base);
1018 in_sdram = running_from_sdram();
1019 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1021 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1022 emif_get_reg_dump(emif_nr, ®s);
1024 debug("EMIF: reg dump not provided\n");
1029 * The user has not provided the register values. We need to
1030 * calculate it based on the timings and the DDR frequency
1032 struct emif_device_details dev_details;
1033 struct emif_regs calculated_regs;
1036 * Get device details:
1037 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1038 * - Obtained from user otherwise
1040 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1041 emif_reset_phy(base);
1042 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1044 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1046 emif_reset_phy(base);
1048 /* Return if no devices on this EMIF */
1049 if (!dev_details.cs0_device_details &&
1050 !dev_details.cs1_device_details) {
1055 * Get device timings:
1056 * - Default timings specified by JESD209-2 if
1057 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1058 * - Obtained from user otherwise
1060 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1061 &dev_details.cs1_device_timings);
1063 /* Calculate the register values */
1064 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1065 regs = &calculated_regs;
1066 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1069 * Initializing the LPDDR2 device can not happen from SDRAM.
1070 * Changing the timing registers in EMIF can happen(going from one
1073 if (!(in_sdram || warm_reset())) {
1074 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1075 lpddr2_init(base, regs);
1077 ddr3_init(base, regs);
1079 if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1080 set_lpmode_selfrefresh(base);
1081 emif_reset_phy(base);
1082 if (omap_revision() == DRA752_ES1_0)
1083 ddr3_sw_leveling(base, regs);
1085 ddr3_leveling(base, regs);
1088 /* Write to the shadow registers */
1089 emif_update_timings(base, regs);
1091 debug("<<do_sdram_init() %x\n", base);
1094 void emif_post_init_config(u32 base)
1096 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1097 u32 omap_rev = omap_revision();
1099 /* reset phy on ES2.0 */
1100 if (omap_rev == OMAP4430_ES2_0)
1101 emif_reset_phy(base);
1103 /* Put EMIF back in smart idle on ES1.0 */
1104 if (omap_rev == OMAP4430_ES1_0)
1105 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1108 void dmm_init(u32 base)
1110 const struct dmm_lisa_map_regs *lisa_map_regs;
1111 u32 i, section, valid;
1113 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1114 emif_get_dmm_regs(&lisa_map_regs);
1116 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1117 u32 section_cnt, sys_addr;
1118 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1122 sys_addr = CONFIG_SYS_SDRAM_BASE;
1123 emif1_size = get_emif_mem_size(EMIF1_BASE);
1124 emif2_size = get_emif_mem_size(EMIF2_BASE);
1125 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1127 if (!emif1_size && !emif2_size)
1130 /* symmetric interleaved section */
1131 if (emif1_size && emif2_size) {
1132 mapped_size = min(emif1_size, emif2_size);
1133 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1134 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1136 section_map |= (sys_addr >> 24) <<
1137 EMIF_SYS_ADDR_SHIFT;
1138 section_map |= get_dmm_section_size_map(mapped_size * 2)
1139 << EMIF_SYS_SIZE_SHIFT;
1140 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1141 emif1_size -= mapped_size;
1142 emif2_size -= mapped_size;
1143 sys_addr += (mapped_size * 2);
1148 * Single EMIF section(we can have a maximum of 1 single EMIF
1149 * section- either EMIF1 or EMIF2 or none, but not both)
1152 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1153 section_map |= get_dmm_section_size_map(emif1_size)
1154 << EMIF_SYS_SIZE_SHIFT;
1156 section_map |= (mapped_size >> 24) <<
1157 EMIF_SDRC_ADDR_SHIFT;
1159 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1163 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1164 section_map |= get_dmm_section_size_map(emif2_size) <<
1165 EMIF_SYS_SIZE_SHIFT;
1167 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1169 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1173 if (section_cnt == 2) {
1174 /* Only 1 section - either symmetric or single EMIF */
1175 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1176 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1177 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1179 /* 2 sections - 1 symmetric, 1 single EMIF */
1180 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1181 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1184 /* TRAP for invalid TILER mappings in section 0 */
1185 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1187 if (omap_revision() >= OMAP4460_ES1_0)
1188 lis_map_regs_calculated.is_ma_present = 1;
1190 lisa_map_regs = &lis_map_regs_calculated;
1192 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1193 (struct dmm_lisa_map_regs *)base;
1195 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1196 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1197 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1198 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1200 writel(lisa_map_regs->dmm_lisa_map_3,
1201 &hw_lisa_map_regs->dmm_lisa_map_3);
1202 writel(lisa_map_regs->dmm_lisa_map_2,
1203 &hw_lisa_map_regs->dmm_lisa_map_2);
1204 writel(lisa_map_regs->dmm_lisa_map_1,
1205 &hw_lisa_map_regs->dmm_lisa_map_1);
1206 writel(lisa_map_regs->dmm_lisa_map_0,
1207 &hw_lisa_map_regs->dmm_lisa_map_0);
1209 if (lisa_map_regs->is_ma_present) {
1211 (struct dmm_lisa_map_regs *)MA_BASE;
1213 writel(lisa_map_regs->dmm_lisa_map_3,
1214 &hw_lisa_map_regs->dmm_lisa_map_3);
1215 writel(lisa_map_regs->dmm_lisa_map_2,
1216 &hw_lisa_map_regs->dmm_lisa_map_2);
1217 writel(lisa_map_regs->dmm_lisa_map_1,
1218 &hw_lisa_map_regs->dmm_lisa_map_1);
1219 writel(lisa_map_regs->dmm_lisa_map_0,
1220 &hw_lisa_map_regs->dmm_lisa_map_0);
1224 * EMIF should be configured only when
1225 * memory is mapped on it. Using emif1_enabled
1226 * and emif2_enabled variables for this.
1230 for (i = 0; i < 4; i++) {
1231 section = __raw_readl(DMM_BASE + i*4);
1232 valid = (section & EMIF_SDRC_MAP_MASK) >>
1233 (EMIF_SDRC_MAP_SHIFT);
1238 } else if (valid == 1) {
1240 } else if (valid == 2) {
1248 * SDRAM initialization:
1249 * SDRAM initialization has two parts:
1250 * 1. Configuring the SDRAM device
1251 * 2. Update the AC timings related parameters in the EMIF module
1252 * (1) should be done only once and should not be done while we are
1253 * running from SDRAM.
1254 * (2) can and should be done more than once if OPP changes.
1255 * Particularly, this may be needed when we boot without SPL and
1256 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1257 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1258 * the frequency. So,
1259 * Doing (1) and (2) makes sense - first time initialization
1260 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1261 * Doing (1) and not (2) doen't make sense
1262 * See do_sdram_init() for the details
1264 void sdram_init(void)
1266 u32 in_sdram, size_prog, size_detect;
1267 u32 sdram_type = emif_sdram_type();
1269 debug(">>sdram_init()\n");
1271 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1274 in_sdram = running_from_sdram();
1275 debug("in_sdram = %d\n", in_sdram);
1278 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1279 bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1280 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1281 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1288 do_sdram_init(EMIF1_BASE);
1291 do_sdram_init(EMIF2_BASE);
1293 if (!(in_sdram || warm_reset())) {
1295 emif_post_init_config(EMIF1_BASE);
1297 emif_post_init_config(EMIF2_BASE);
1300 /* for the shadow registers to take effect */
1301 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1304 /* Do some testing after the init */
1306 size_prog = omap_sdram_size();
1307 size_prog = log_2_n_round_down(size_prog);
1308 size_prog = (1 << size_prog);
1310 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1312 /* Compare with the size programmed */
1313 if (size_detect != size_prog) {
1314 printf("SDRAM: identified size not same as expected"
1315 " size identified: %x expected: %x\n",
1319 debug("get_ram_size() successful");
1322 debug("<<sdram_init()\n");