git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         if (!is_dra72x())
  41                 set_lpmode_selfrefresh(EMIF2_BASE);
  42 }
  43
  44 inline u32 emif_num(u32 base)
  45 {
  46         if (base == EMIF1_BASE)
  47                 return 1;
  48         else if (base == EMIF2_BASE)
  49                 return 2;
  50         else
  51                 return 0;
  52 }
  53
  54 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  55 {
  56         u32 mr;
  57         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  58
  59         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  60         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  61         if (omap_revision() == OMAP4430_ES2_0)
  62                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  63         else
  64                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  65         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  66               cs, mr_addr, mr);
  67         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  68             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  69             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  70                 return mr & 0xff;
  71         else
  72                 return mr;
  73 }
  74
  75 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  76 {
  77         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  78
  79         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  80         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  81         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  82 }
  83
  84 void emif_reset_phy(u32 base)
  85 {
  86         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  87         u32 iodft;
  88
  89         iodft = readl(&emif->emif_iodft_tlgc);
  90         iodft |= EMIF_REG_RESET_PHY_MASK;
  91         writel(iodft, &emif->emif_iodft_tlgc);
  92 }
  93
  94 static void do_lpddr2_init(u32 base, u32 cs)
  95 {
  96         u32 mr_addr;
  97         const struct lpddr2_mr_regs *mr_regs;
  98
  99         get_lpddr2_mr_regs(&mr_regs);
 100         /* Wait till device auto initialization is complete */
 101         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 102                 ;
 103         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 104         /*
 105          * tZQINIT = 1 us
 106          * Enough loops assuming a maximum of 2GHz
 107          */
 108
 109         sdelay(2000);
 110
 111         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 112         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 113
 114         /*
 115          * Enable refresh along with writing MR2
 116          * Encoding of RL in MR2 is (RL - 2)
 117          */
 118         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 119         set_mr(base, cs, mr_addr, mr_regs->mr2);
 120
 121         if (mr_regs->mr3 > 0)
 122                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 123 }
 124
 125 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 126 {
 127         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 128
 129         /* Not NVM */
 130         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 131
 132         /*
 133          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 134          * when EMIF_SDRAM_CONFIG register is written
 135          */
 136         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 137
 138         /*
 139          * Set the SDRAM_CONFIG and PHY_CTRL for the
 140          * un-locked frequency & default RL
 141          */
 142         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 143         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 144
 145         do_ext_phy_settings(base, regs);
 146
 147         do_lpddr2_init(base, CS0);
 148         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 149                 do_lpddr2_init(base, CS1);
 150
 151         writel(regs->sdram_config, &emif->emif_sdram_config);
 152         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 153
 154         /* Enable refresh now */
 155         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 156
 157         }
 158
 159 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 160 {
 161 }
 162
 163 void emif_update_timings(u32 base, const struct emif_regs *regs)
 164 {
 165         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 166
 167         if (!is_dra7xx())
 168                 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 169         else
 170                 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
 171
 172         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 173         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 174         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 175         if (omap_revision() == OMAP4430_ES1_0) {
 176                 /* ES1 bug EMIF should be in force idle during freq_update */
 177                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 178         } else {
 179                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 180                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 181         }
 182         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 183         writel(regs->zq_config, &emif->emif_zq_config);
 184         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 185         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 186
 187         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 188                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 189                         &emif->emif_l3_config);
 190         } else if (omap_revision() >= OMAP4460_ES1_0) {
 191                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 192                         &emif->emif_l3_config);
 193         } else {
 194                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 195                         &emif->emif_l3_config);
 196         }
 197 }
 198
 199 #ifndef CONFIG_OMAP44XX
 200 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 201 {
 202         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 203
 204         /* keep sdram in self-refresh */
 205         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 206                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 207         __udelay(130);
 208
 209         /*
 210          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 211          * Invert clock adds an additional half cycle delay on the
 212          * command interface.  The additional half cycle, is usually
 213          * meant to enable leveling in the situation that DQS is later
 214          * than CK on the board.It also helps provide some additional
 215          * margin for leveling.
 216          */
 217         writel(regs->emif_ddr_phy_ctlr_1,
 218                &emif->emif_ddr_phy_ctrl_1);
 219
 220         writel(regs->emif_ddr_phy_ctlr_1,
 221                &emif->emif_ddr_phy_ctrl_1_shdw);
 222         __udelay(130);
 223
 224         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 225                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 226
 227         /* Launch Full leveling */
 228         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 229
 230         /* Wait till full leveling is complete */
 231         readl(&emif->emif_rd_wr_lvl_ctl);
 232               __udelay(130);
 233
 234         /* Read data eye leveling no of samples */
 235         config_data_eye_leveling_samples(base);
 236
 237         /*
 238          * Launch 8 incremental WR_LVL- to compensate for
 239          * PHY limitation.
 240          */
 241         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 242                &emif->emif_rd_wr_lvl_ctl);
 243
 244         __udelay(130);
 245
 246         /* Launch Incremental leveling */
 247         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 248                __udelay(130);
 249 }
 250
 251 static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 252 {
 253         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 254         u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
 255         u32 reg, i, phy;
 256
 257         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
 258         phy = readl(&emif->emif_ddr_phy_ctrl_1);
 259
 260         /* Update PHY_REG_RDDQS_RATIO */
 261         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
 262         if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
 263                 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
 264                         reg = readl(emif_phy_status++);
 265                         writel(reg, emif_ext_phy_ctrl_reg++);
 266                         writel(reg, emif_ext_phy_ctrl_reg++);
 267                 }
 268
 269         /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 270         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
 271         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
 272         if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
 273                 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
 274                         reg = readl(emif_phy_status++);
 275                         writel(reg, emif_ext_phy_ctrl_reg++);
 276                         writel(reg, emif_ext_phy_ctrl_reg++);
 277                 }
 278
 279         /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 280         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
 281         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
 282         if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
 283                 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
 284                         reg = readl(emif_phy_status++);
 285                         writel(reg, emif_ext_phy_ctrl_reg++);
 286                         writel(reg, emif_ext_phy_ctrl_reg++);
 287                 }
 288
 289         /* Disable Leveling */
 290         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 291         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 292         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 293 }
 294
 295 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 296 {
 297         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 298
 299         /* Clear Error Status */
 300         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
 301                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 302                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 303
 304         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
 305                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 306                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 307
 308         /* Disable refreshed before leveling */
 309         clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
 310                         EMIF_REG_INITREF_DIS_MASK);
 311
 312         /* Start Full leveling */
 313         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 314
 315         __udelay(300);
 316
 317         /* Check for leveling timeout */
 318         if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
 319                 printf("Leveling timeout on EMIF%d\n", emif_num(base));
 320                 return;
 321         }
 322
 323         /* Enable refreshes after leveling */
 324         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 325
 326         debug("HW leveling success\n");
 327         /*
 328          * Update slave ratios in EXT_PHY_CTRLx registers
 329          * as per HW leveling output
 330          */
 331         update_hwleveling_output(base, regs);
 332 }
 333
 334 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
 335 {
 336         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 337
 338         if (warm_reset()) {
 339                 emif_reset_phy(base);
 340                 writel(0x0, &emif->emif_pwr_mgmt_ctrl);
 341         }
 342         do_ext_phy_settings(base, regs);
 343
 344         writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
 345                &emif->emif_sdram_ref_ctrl);
 346         /* Update timing registers */
 347         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 348         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 349         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 350
 351         writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
 352         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 353         writel(regs->zq_config, &emif->emif_zq_config);
 354         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 355         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 356         writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
 357
 358         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 359         writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
 360
 361         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 362
 363         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 364         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 365
 366         __udelay(1000);
 367
 368         writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
 369
 370         if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
 371                 dra7_ddr3_leveling(base, regs);
 372 }
 373
 374 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
 375 {
 376         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 377
 378         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 379         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 380         /*
 381          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 382          * and RL =7. As the default values of the Mode Registers are not
 383          * defined, contents of mode Registers must be fully initialized.
 384          * H/W takes care of this initialization
 385          */
 386         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 387
 388         /* Update timing registers */
 389         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 390         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 391         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 392
 393         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 394
 395         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 396         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 397         do_ext_phy_settings(base, regs);
 398
 399         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 400         omap5_ddr3_leveling(base, regs);
 401 }
 402
 403 static void ddr3_init(u32 base, const struct emif_regs *regs)
 404 {
 405         if (is_omap54xx())
 406                 omap5_ddr3_init(base, regs);
 407         else
 408                 dra7_ddr3_init(base, regs);
 409 }
 410 #endif
 411
 412 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 413 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 414
 415 /*
 416  * Organization and refresh requirements for LPDDR2 devices of different
 417  * types and densities. Derived from JESD209-2 section 2.4
 418  */
 419 const struct lpddr2_addressing addressing_table[] = {
 420         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 421         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 422         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 423         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 424         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 425         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 426         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 427         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 428         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 429         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 430         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 431 };
 432
 433 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 434         8,                      /* 64Mb */
 435         16,                     /* 128Mb */
 436         32,                     /* 256Mb */
 437         64,                     /* 512Mb */
 438         128,                    /* 1Gb   */
 439         256,                    /* 2Gb   */
 440         512,                    /* 4Gb   */
 441         1024,                   /* 8Gb   */
 442         2048,                   /* 16Gb  */
 443         4096                    /* 32Gb  */
 444 };
 445
 446 /*
 447  * Calculate the period of DDR clock from frequency value and set the
 448  * denominator and numerator in global variables for easy access later
 449  */
 450 static void set_ddr_clk_period(u32 freq)
 451 {
 452         /*
 453          * period = 1/freq
 454          * period_in_ns = 10^9/freq
 455          */
 456         *T_num = 1000000000;
 457         *T_den = freq;
 458         cancel_out(T_num, T_den, 200);
 459
 460 }
 461
 462 /*
 463  * Convert time in nano seconds to number of cycles of DDR clock
 464  */
 465 static inline u32 ns_2_cycles(u32 ns)
 466 {
 467         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 468 }
 469
 470 /*
 471  * ns_2_cycles with the difference that the time passed is 2 times the actual
 472  * value(to avoid fractions). The cycles returned is for the original value of
 473  * the timing parameter
 474  */
 475 static inline u32 ns_x2_2_cycles(u32 ns)
 476 {
 477         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 478 }
 479
 480 /*
 481  * Find addressing table index based on the device's type(S2 or S4) and
 482  * density
 483  */
 484 s8 addressing_table_index(u8 type, u8 density, u8 width)
 485 {
 486         u8 index;
 487         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 488                 return -1;
 489
 490         /*
 491          * Look at the way ADDR_TABLE_INDEX* values have been defined
 492          * in emif.h compared to LPDDR2_DENSITY_* values
 493          * The table is layed out in the increasing order of density
 494          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 495          * at the end
 496          */
 497         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 498                 index = ADDR_TABLE_INDEX1GS2;
 499         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 500                 index = ADDR_TABLE_INDEX2GS2;
 501         else
 502                 index = density;
 503
 504         debug("emif: addressing table index %d\n", index);
 505
 506         return index;
 507 }
 508
 509 /*
 510  * Find the the right timing table from the array of timing
 511  * tables of the device using DDR clock frequency
 512  */
 513 static const struct lpddr2_ac_timings *get_timings_table(const struct
 514                         lpddr2_ac_timings const *const *device_timings,
 515                         u32 freq)
 516 {
 517         u32 i, temp, freq_nearest;
 518         const struct lpddr2_ac_timings *timings = 0;
 519
 520         emif_assert(freq <= MAX_LPDDR2_FREQ);
 521         emif_assert(device_timings);
 522
 523         /*
 524          * Start with the maximum allowed frequency - that is always safe
 525          */
 526         freq_nearest = MAX_LPDDR2_FREQ;
 527         /*
 528          * Find the timings table that has the max frequency value:
 529          *   i.  Above or equal to the DDR frequency - safe
 530          *   ii. The lowest that satisfies condition (i) - optimal
 531          */
 532         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 533                 temp = device_timings[i]->max_freq;
 534                 if ((temp >= freq) && (temp <= freq_nearest)) {
 535                         freq_nearest = temp;
 536                         timings = device_timings[i];
 537                 }
 538         }
 539         debug("emif: timings table: %d\n", freq_nearest);
 540         return timings;
 541 }
 542
 543 /*
 544  * Finds the value of emif_sdram_config_reg
 545  * All parameters are programmed based on the device on CS0.
 546  * If there is a device on CS1, it will be same as that on CS0 or
 547  * it will be NVM. We don't support NVM yet.
 548  * If cs1_device pointer is NULL it is assumed that there is no device
 549  * on CS1
 550  */
 551 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 552                                 const struct lpddr2_device_details *cs1_device,
 553                                 const struct lpddr2_addressing *addressing,
 554                                 u8 RL)
 555 {
 556         u32 config_reg = 0;
 557
 558         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 559         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 560                         EMIF_REG_IBANK_POS_SHIFT;
 561
 562         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 563
 564         config_reg |= RL << EMIF_REG_CL_SHIFT;
 565
 566         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 567                         EMIF_REG_ROWSIZE_SHIFT;
 568
 569         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 570
 571         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 572                         EMIF_REG_EBANK_SHIFT;
 573
 574         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 575                         EMIF_REG_PAGESIZE_SHIFT;
 576
 577         return config_reg;
 578 }
 579
 580 static u32 get_sdram_ref_ctrl(u32 freq,
 581                               const struct lpddr2_addressing *addressing)
 582 {
 583         u32 ref_ctrl = 0, val = 0, freq_khz;
 584         freq_khz = freq / 1000;
 585         /*
 586          * refresh rate to be set is 'tREFI * freq in MHz
 587          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 588          */
 589         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 590         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 591
 592         return ref_ctrl;
 593 }
 594
 595 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 596                                const struct lpddr2_min_tck *min_tck,
 597                                const struct lpddr2_addressing *addressing)
 598 {
 599         u32 tim1 = 0, val = 0;
 600         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 601         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 602
 603         if (addressing->num_banks == BANKS8)
 604                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 605                                                         (4 * (*T_num)) - 1;
 606         else
 607                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 608
 609         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 610
 611         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 612         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 613
 614         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 615         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 616
 617         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 618         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 619
 620         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 621         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 622
 623         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 624         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 625
 626         return tim1;
 627 }
 628
 629 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 630                                const struct lpddr2_min_tck *min_tck)
 631 {
 632         u32 tim2 = 0, val = 0;
 633         val = max(min_tck->tCKE, timings->tCKE) - 1;
 634         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 635
 636         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 637         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 638
 639         /*
 640          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 641          * same value
 642          */
 643         val = ns_2_cycles(timings->tXSR) - 1;
 644         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 645         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 646
 647         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 648         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 649
 650         return tim2;
 651 }
 652
 653 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 654                                const struct lpddr2_min_tck *min_tck,
 655                                const struct lpddr2_addressing *addressing)
 656 {
 657         u32 tim3 = 0, val = 0;
 658         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 659         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 660
 661         val = ns_2_cycles(timings->tRFCab) - 1;
 662         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 663
 664         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 665         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 666
 667         val = ns_2_cycles(timings->tZQCS) - 1;
 668         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 669
 670         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 671         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 672
 673         return tim3;
 674 }
 675
 676 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 677                              const struct lpddr2_addressing *addressing,
 678                              u8 volt_ramp)
 679 {
 680         u32 zq = 0, val = 0;
 681         if (volt_ramp)
 682                 val =
 683                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 684                     addressing->t_REFI_us_x10;
 685         else
 686                 val =
 687                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 688                     addressing->t_REFI_us_x10;
 689         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 690
 691         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 692
 693         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 694
 695         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 696
 697         /*
 698          * Assuming that two chipselects have a single calibration resistor
 699          * If there are indeed two calibration resistors, then this flag should
 700          * be enabled to take advantage of dual calibration feature.
 701          * This data should ideally come from board files. But considering
 702          * that none of the boards today have calibration resistors per CS,
 703          * it would be an unnecessary overhead.
 704          */
 705         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 706
 707         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 708
 709         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 710
 711         return zq;
 712 }
 713
 714 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 715                                  const struct lpddr2_addressing *addressing,
 716                                  u8 is_derated)
 717 {
 718         u32 alert = 0, interval;
 719         interval =
 720             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 721         if (is_derated)
 722                 interval *= 4;
 723         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 724
 725         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 726
 727         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 728
 729         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 730
 731         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 732
 733         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 734
 735         return alert;
 736 }
 737
 738 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 739 {
 740         u32 idle = 0, val = 0;
 741         if (volt_ramp)
 742                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 743         else
 744                 /*Maximum value in normal conditions - suggested by hw team */
 745                 val = 0x1FF;
 746         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 747
 748         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 749
 750         return idle;
 751 }
 752
 753 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 754 {
 755         u32 phy = 0, val = 0;
 756
 757         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 758
 759         if (freq <= 100000000)
 760                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 761         else if (freq <= 200000000)
 762                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 763         else
 764                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 765         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 766
 767         /* Other fields are constant magic values. Hardcode them together */
 768         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 769                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 770
 771         return phy;
 772 }
 773
 774 static u32 get_emif_mem_size(u32 base)
 775 {
 776         u32 size_mbytes = 0, temp;
 777         struct emif_device_details dev_details;
 778         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 779         u32 emif_nr = emif_num(base);
 780
 781         emif_reset_phy(base);
 782         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 783                                                 &cs0_dev_details);
 784         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 785                                                 &cs1_dev_details);
 786         emif_reset_phy(base);
 787
 788         if (dev_details.cs0_device_details) {
 789                 temp = dev_details.cs0_device_details->density;
 790                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 791         }
 792
 793         if (dev_details.cs1_device_details) {
 794                 temp = dev_details.cs1_device_details->density;
 795                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 796         }
 797         /* convert to bytes */
 798         return size_mbytes << 20;
 799 }
 800
 801 /* Gets the encoding corresponding to a given DMM section size */
 802 u32 get_dmm_section_size_map(u32 section_size)
 803 {
 804         /*
 805          * Section size mapping:
 806          * 0x0: 16-MiB section
 807          * 0x1: 32-MiB section
 808          * 0x2: 64-MiB section
 809          * 0x3: 128-MiB section
 810          * 0x4: 256-MiB section
 811          * 0x5: 512-MiB section
 812          * 0x6: 1-GiB section
 813          * 0x7: 2-GiB section
 814          */
 815         section_size >>= 24; /* divide by 16 MB */
 816         return log_2_n_round_down(section_size);
 817 }
 818
 819 static void emif_calculate_regs(
 820                 const struct emif_device_details *emif_dev_details,
 821                 u32 freq, struct emif_regs *regs)
 822 {
 823         u32 temp, sys_freq;
 824         const struct lpddr2_addressing *addressing;
 825         const struct lpddr2_ac_timings *timings;
 826         const struct lpddr2_min_tck *min_tck;
 827         const struct lpddr2_device_details *cs0_dev_details =
 828                                         emif_dev_details->cs0_device_details;
 829         const struct lpddr2_device_details *cs1_dev_details =
 830                                         emif_dev_details->cs1_device_details;
 831         const struct lpddr2_device_timings *cs0_dev_timings =
 832                                         emif_dev_details->cs0_device_timings;
 833
 834         emif_assert(emif_dev_details);
 835         emif_assert(regs);
 836         /*
 837          * You can not have a device on CS1 without one on CS0
 838          * So configuring EMIF without a device on CS0 doesn't
 839          * make sense
 840          */
 841         emif_assert(cs0_dev_details);
 842         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 843         /*
 844          * If there is a device on CS1 it should be same type as CS0
 845          * (or NVM. But NVM is not supported in this driver yet)
 846          */
 847         emif_assert((cs1_dev_details == NULL) ||
 848                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 849                     (cs0_dev_details->type == cs1_dev_details->type));
 850         emif_assert(freq <= MAX_LPDDR2_FREQ);
 851
 852         set_ddr_clk_period(freq);
 853
 854         /*
 855          * The device on CS0 is used for all timing calculations
 856          * There is only one set of registers for timings per EMIF. So, if the
 857          * second CS(CS1) has a device, it should have the same timings as the
 858          * device on CS0
 859          */
 860         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 861         emif_assert(timings);
 862         min_tck = cs0_dev_timings->min_tck;
 863
 864         temp = addressing_table_index(cs0_dev_details->type,
 865                                       cs0_dev_details->density,
 866                                       cs0_dev_details->io_width);
 867
 868         emif_assert((temp >= 0));
 869         addressing = &(addressing_table[temp]);
 870         emif_assert(addressing);
 871
 872         sys_freq = get_sys_clk_freq();
 873
 874         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 875                                                         cs1_dev_details,
 876                                                         addressing, RL_BOOT);
 877
 878         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 879                                                 cs1_dev_details,
 880                                                 addressing, RL_FINAL);
 881
 882         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 883
 884         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 885
 886         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 887
 888         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 889
 890         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 891
 892         regs->temp_alert_config =
 893             get_temp_alert_config(cs1_dev_details, addressing, 0);
 894
 895         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 896                                             LPDDR2_VOLTAGE_STABLE);
 897
 898         regs->emif_ddr_phy_ctlr_1_init =
 899                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 900
 901         regs->emif_ddr_phy_ctlr_1 =
 902                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 903
 904         regs->freq = freq;
 905
 906         print_timing_reg(regs->sdram_config_init);
 907         print_timing_reg(regs->sdram_config);
 908         print_timing_reg(regs->ref_ctrl);
 909         print_timing_reg(regs->sdram_tim1);
 910         print_timing_reg(regs->sdram_tim2);
 911         print_timing_reg(regs->sdram_tim3);
 912         print_timing_reg(regs->read_idle_ctrl);
 913         print_timing_reg(regs->temp_alert_config);
 914         print_timing_reg(regs->zq_config);
 915         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 916         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 917 }
 918 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 919
 920 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 921 const char *get_lpddr2_type(u8 type_id)
 922 {
 923         switch (type_id) {
 924         case LPDDR2_TYPE_S4:
 925                 return "LPDDR2-S4";
 926         case LPDDR2_TYPE_S2:
 927                 return "LPDDR2-S2";
 928         default:
 929                 return NULL;
 930         }
 931 }
 932
 933 const char *get_lpddr2_io_width(u8 width_id)
 934 {
 935         switch (width_id) {
 936         case LPDDR2_IO_WIDTH_8:
 937                 return "x8";
 938         case LPDDR2_IO_WIDTH_16:
 939                 return "x16";
 940         case LPDDR2_IO_WIDTH_32:
 941                 return "x32";
 942         default:
 943                 return NULL;
 944         }
 945 }
 946
 947 const char *get_lpddr2_manufacturer(u32 manufacturer)
 948 {
 949         switch (manufacturer) {
 950         case LPDDR2_MANUFACTURER_SAMSUNG:
 951                 return "Samsung";
 952         case LPDDR2_MANUFACTURER_QIMONDA:
 953                 return "Qimonda";
 954         case LPDDR2_MANUFACTURER_ELPIDA:
 955                 return "Elpida";
 956         case LPDDR2_MANUFACTURER_ETRON:
 957                 return "Etron";
 958         case LPDDR2_MANUFACTURER_NANYA:
 959                 return "Nanya";
 960         case LPDDR2_MANUFACTURER_HYNIX:
 961                 return "Hynix";
 962         case LPDDR2_MANUFACTURER_MOSEL:
 963                 return "Mosel";
 964         case LPDDR2_MANUFACTURER_WINBOND:
 965                 return "Winbond";
 966         case LPDDR2_MANUFACTURER_ESMT:
 967                 return "ESMT";
 968         case LPDDR2_MANUFACTURER_SPANSION:
 969                 return "Spansion";
 970         case LPDDR2_MANUFACTURER_SST:
 971                 return "SST";
 972         case LPDDR2_MANUFACTURER_ZMOS:
 973                 return "ZMOS";
 974         case LPDDR2_MANUFACTURER_INTEL:
 975                 return "Intel";
 976         case LPDDR2_MANUFACTURER_NUMONYX:
 977                 return "Numonyx";
 978         case LPDDR2_MANUFACTURER_MICRON:
 979                 return "Micron";
 980         default:
 981                 return NULL;
 982         }
 983 }
 984
 985 static void display_sdram_details(u32 emif_nr, u32 cs,
 986                                   struct lpddr2_device_details *device)
 987 {
 988         const char *mfg_str;
 989         const char *type_str;
 990         char density_str[10];
 991         u32 density;
 992
 993         debug("EMIF%d CS%d\t", emif_nr, cs);
 994
 995         if (!device) {
 996                 debug("None\n");
 997                 return;
 998         }
 999
1000         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
1001         type_str = get_lpddr2_type(device->type);
1002
1003         density = lpddr2_density_2_size_in_mbytes[device->density];
1004         if ((density / 1024 * 1024) == density) {
1005                 density /= 1024;
1006                 sprintf(density_str, "%d GB", density);
1007         } else
1008                 sprintf(density_str, "%d MB", density);
1009         if (mfg_str && type_str)
1010                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
1011 }
1012
1013 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
1014                                   struct lpddr2_device_details *lpddr2_device)
1015 {
1016         u32 mr = 0, temp;
1017
1018         mr = get_mr(base, cs, LPDDR2_MR0);
1019         if (mr > 0xFF) {
1020                 /* Mode register value bigger than 8 bit */
1021                 return 0;
1022         }
1023
1024         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
1025         if (temp) {
1026                 /* Not SDRAM */
1027                 return 0;
1028         }
1029         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
1030
1031         if (temp) {
1032                 /* DNV supported - But DNV is only supported for NVM */
1033                 return 0;
1034         }
1035
1036         mr = get_mr(base, cs, LPDDR2_MR4);
1037         if (mr > 0xFF) {
1038                 /* Mode register value bigger than 8 bit */
1039                 return 0;
1040         }
1041
1042         mr = get_mr(base, cs, LPDDR2_MR5);
1043         if (mr > 0xFF) {
1044                 /* Mode register value bigger than 8 bit */
1045                 return 0;
1046         }
1047
1048         if (!get_lpddr2_manufacturer(mr)) {
1049                 /* Manufacturer not identified */
1050                 return 0;
1051         }
1052         lpddr2_device->manufacturer = mr;
1053
1054         mr = get_mr(base, cs, LPDDR2_MR6);
1055         if (mr >= 0xFF) {
1056                 /* Mode register value bigger than 8 bit */
1057                 return 0;
1058         }
1059
1060         mr = get_mr(base, cs, LPDDR2_MR7);
1061         if (mr >= 0xFF) {
1062                 /* Mode register value bigger than 8 bit */
1063                 return 0;
1064         }
1065
1066         mr = get_mr(base, cs, LPDDR2_MR8);
1067         if (mr >= 0xFF) {
1068                 /* Mode register value bigger than 8 bit */
1069                 return 0;
1070         }
1071
1072         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1073         if (!get_lpddr2_type(temp)) {
1074                 /* Not SDRAM */
1075                 return 0;
1076         }
1077         lpddr2_device->type = temp;
1078
1079         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1080         if (temp > LPDDR2_DENSITY_32Gb) {
1081                 /* Density not supported */
1082                 return 0;
1083         }
1084         lpddr2_device->density = temp;
1085
1086         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1087         if (!get_lpddr2_io_width(temp)) {
1088                 /* IO width unsupported value */
1089                 return 0;
1090         }
1091         lpddr2_device->io_width = temp;
1092
1093         /*
1094          * If all the above tests pass we should
1095          * have a device on this chip-select
1096          */
1097         return 1;
1098 }
1099
1100 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1101                         struct lpddr2_device_details *lpddr2_dev_details)
1102 {
1103         u32 phy;
1104         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1105
1106         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1107
1108         if (!lpddr2_dev_details)
1109                 return NULL;
1110
1111         /* Do the minimum init for mode register accesses */
1112         if (!(running_from_sdram() || warm_reset())) {
1113                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1114                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1115         }
1116
1117         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1118                 return NULL;
1119
1120         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1121
1122         return lpddr2_dev_details;
1123 }
1124 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1125
1126 static void do_sdram_init(u32 base)
1127 {
1128         const struct emif_regs *regs;
1129         u32 in_sdram, emif_nr;
1130
1131         debug(">>do_sdram_init() %x\n", base);
1132
1133         in_sdram = running_from_sdram();
1134         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1135
1136 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1137         emif_get_reg_dump(emif_nr, &regs);
1138         if (!regs) {
1139                 debug("EMIF: reg dump not provided\n");
1140                 return;
1141         }
1142 #else
1143         /*
1144          * The user has not provided the register values. We need to
1145          * calculate it based on the timings and the DDR frequency
1146          */
1147         struct emif_device_details dev_details;
1148         struct emif_regs calculated_regs;
1149
1150         /*
1151          * Get device details:
1152          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1153          * - Obtained from user otherwise
1154          */
1155         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1156         emif_reset_phy(base);
1157         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1158                                                 &cs0_dev_details);
1159         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1160                                                 &cs1_dev_details);
1161         emif_reset_phy(base);
1162
1163         /* Return if no devices on this EMIF */
1164         if (!dev_details.cs0_device_details &&
1165             !dev_details.cs1_device_details) {
1166                 return;
1167         }
1168
1169         /*
1170          * Get device timings:
1171          * - Default timings specified by JESD209-2 if
1172          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1173          * - Obtained from user otherwise
1174          */
1175         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1176                                 &dev_details.cs1_device_timings);
1177
1178         /* Calculate the register values */
1179         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1180         regs = &calculated_regs;
1181 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1182
1183         /*
1184          * Initializing the DDR device can not happen from SDRAM.
1185          * Changing the timing registers in EMIF can happen(going from one
1186          * OPP to another)
1187          */
1188         if (!in_sdram && (!warm_reset() || is_dra7xx())) {
1189                 if (emif_sdram_type(regs->sdram_config) ==
1190                     EMIF_SDRAM_TYPE_LPDDR2)
1191                         lpddr2_init(base, regs);
1192 #ifndef CONFIG_OMAP44XX
1193                 else
1194                         ddr3_init(base, regs);
1195 #endif
1196         }
1197 #ifdef CONFIG_OMAP54X
1198         if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
1199             EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
1200                 set_lpmode_selfrefresh(base);
1201                 emif_reset_phy(base);
1202                 omap5_ddr3_leveling(base, regs);
1203         }
1204 #endif
1205
1206         /* Write to the shadow registers */
1207         emif_update_timings(base, regs);
1208
1209         debug("<<do_sdram_init() %x\n", base);
1210 }
1211
1212 void emif_post_init_config(u32 base)
1213 {
1214         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1215         u32 omap_rev = omap_revision();
1216
1217         /* reset phy on ES2.0 */
1218         if (omap_rev == OMAP4430_ES2_0)
1219                 emif_reset_phy(base);
1220
1221         /* Put EMIF back in smart idle on ES1.0 */
1222         if (omap_rev == OMAP4430_ES1_0)
1223                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1224 }
1225
1226 void dmm_init(u32 base)
1227 {
1228         const struct dmm_lisa_map_regs *lisa_map_regs;
1229         u32 i, section, valid;
1230
1231 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1232         emif_get_dmm_regs(&lisa_map_regs);
1233 #else
1234         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1235         u32 section_cnt, sys_addr;
1236         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1237
1238         mapped_size = 0;
1239         section_cnt = 3;
1240         sys_addr = CONFIG_SYS_SDRAM_BASE;
1241         emif1_size = get_emif_mem_size(EMIF1_BASE);
1242         emif2_size = get_emif_mem_size(EMIF2_BASE);
1243         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1244
1245         if (!emif1_size && !emif2_size)
1246                 return;
1247
1248         /* symmetric interleaved section */
1249         if (emif1_size && emif2_size) {
1250                 mapped_size = min(emif1_size, emif2_size);
1251                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1252                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1253                 /* only MSB */
1254                 section_map |= (sys_addr >> 24) <<
1255                                 EMIF_SYS_ADDR_SHIFT;
1256                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1257                                 << EMIF_SYS_SIZE_SHIFT;
1258                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1259                 emif1_size -= mapped_size;
1260                 emif2_size -= mapped_size;
1261                 sys_addr += (mapped_size * 2);
1262                 section_cnt--;
1263         }
1264
1265         /*
1266          * Single EMIF section(we can have a maximum of 1 single EMIF
1267          * section- either EMIF1 or EMIF2 or none, but not both)
1268          */
1269         if (emif1_size) {
1270                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1271                 section_map |= get_dmm_section_size_map(emif1_size)
1272                                 << EMIF_SYS_SIZE_SHIFT;
1273                 /* only MSB */
1274                 section_map |= (mapped_size >> 24) <<
1275                                 EMIF_SDRC_ADDR_SHIFT;
1276                 /* only MSB */
1277                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1278                 section_cnt--;
1279         }
1280         if (emif2_size) {
1281                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1282                 section_map |= get_dmm_section_size_map(emif2_size) <<
1283                                 EMIF_SYS_SIZE_SHIFT;
1284                 /* only MSB */
1285                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1286                 /* only MSB */
1287                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1288                 section_cnt--;
1289         }
1290
1291         if (section_cnt == 2) {
1292                 /* Only 1 section - either symmetric or single EMIF */
1293                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1294                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1295                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1296         } else {
1297                 /* 2 sections - 1 symmetric, 1 single EMIF */
1298                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1299                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1300         }
1301
1302         /* TRAP for invalid TILER mappings in section 0 */
1303         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1304
1305         if (omap_revision() >= OMAP4460_ES1_0)
1306                 lis_map_regs_calculated.is_ma_present = 1;
1307
1308         lisa_map_regs = &lis_map_regs_calculated;
1309 #endif
1310         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1311             (struct dmm_lisa_map_regs *)base;
1312
1313         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1314         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1315         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1316         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1317
1318         writel(lisa_map_regs->dmm_lisa_map_3,
1319                 &hw_lisa_map_regs->dmm_lisa_map_3);
1320         writel(lisa_map_regs->dmm_lisa_map_2,
1321                 &hw_lisa_map_regs->dmm_lisa_map_2);
1322         writel(lisa_map_regs->dmm_lisa_map_1,
1323                 &hw_lisa_map_regs->dmm_lisa_map_1);
1324         writel(lisa_map_regs->dmm_lisa_map_0,
1325                 &hw_lisa_map_regs->dmm_lisa_map_0);
1326
1327         if (lisa_map_regs->is_ma_present) {
1328                 hw_lisa_map_regs =
1329                     (struct dmm_lisa_map_regs *)MA_BASE;
1330
1331                 writel(lisa_map_regs->dmm_lisa_map_3,
1332                         &hw_lisa_map_regs->dmm_lisa_map_3);
1333                 writel(lisa_map_regs->dmm_lisa_map_2,
1334                         &hw_lisa_map_regs->dmm_lisa_map_2);
1335                 writel(lisa_map_regs->dmm_lisa_map_1,
1336                         &hw_lisa_map_regs->dmm_lisa_map_1);
1337                 writel(lisa_map_regs->dmm_lisa_map_0,
1338                         &hw_lisa_map_regs->dmm_lisa_map_0);
1339
1340                 setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
1341         }
1342
1343         /*
1344          * EMIF should be configured only when
1345          * memory is mapped on it. Using emif1_enabled
1346          * and emif2_enabled variables for this.
1347          */
1348         emif1_enabled = 0;
1349         emif2_enabled = 0;
1350         for (i = 0; i < 4; i++) {
1351                 section = __raw_readl(DMM_BASE + i*4);
1352                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1353                         (EMIF_SDRC_MAP_SHIFT);
1354                 if (valid == 3) {
1355                         emif1_enabled = 1;
1356                         emif2_enabled = 1;
1357                         break;
1358                 }
1359
1360                 if (valid == 1)
1361                         emif1_enabled = 1;
1362
1363                 if (valid == 2)
1364                         emif2_enabled = 1;
1365         }
1366 }
1367
1368 static void do_bug0039_workaround(u32 base)
1369 {
1370         u32 val, i, clkctrl;
1371         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1372         const struct read_write_regs *bug_00339_regs;
1373         u32 iterations;
1374         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1375         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1376
1377         if (is_dra7xx())
1378                 phy_status_base++;
1379
1380         bug_00339_regs = get_bug_regs(&iterations);
1381
1382         /* Put EMIF in to idle */
1383         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1384         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1385
1386         /* Copy the phy status registers in to phy ctrl shadow registers */
1387         for (i = 0; i < iterations; i++) {
1388                 val = __raw_readl(phy_status_base +
1389                                   bug_00339_regs[i].read_reg - 1);
1390
1391                 __raw_writel(val, phy_ctrl_base +
1392                              ((bug_00339_regs[i].write_reg - 1) << 1));
1393
1394                 __raw_writel(val, phy_ctrl_base +
1395                              (bug_00339_regs[i].write_reg << 1) - 1);
1396         }
1397
1398         /* Disable leveling */
1399         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1400
1401         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1402 }
1403
1404 /*
1405  * SDRAM initialization:
1406  * SDRAM initialization has two parts:
1407  * 1. Configuring the SDRAM device
1408  * 2. Update the AC timings related parameters in the EMIF module
1409  * (1) should be done only once and should not be done while we are
1410  * running from SDRAM.
1411  * (2) can and should be done more than once if OPP changes.
1412  * Particularly, this may be needed when we boot without SPL and
1413  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1414  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1415  * the frequency. So,
1416  * Doing (1) and (2) makes sense - first time initialization
1417  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1418  * Doing (1) and not (2) doen't make sense
1419  * See do_sdram_init() for the details
1420  */
1421 void sdram_init(void)
1422 {
1423         u32 in_sdram, size_prog, size_detect;
1424         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1425         u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
1426
1427         debug(">>sdram_init()\n");
1428
1429         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1430                 return;
1431
1432         in_sdram = running_from_sdram();
1433         debug("in_sdram = %d\n", in_sdram);
1434
1435         if (!in_sdram) {
1436                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1437                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1438                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1439                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1440         }
1441
1442         if (!in_sdram)
1443                 dmm_init(DMM_BASE);
1444
1445         if (emif1_enabled)
1446                 do_sdram_init(EMIF1_BASE);
1447
1448         if (emif2_enabled)
1449                 do_sdram_init(EMIF2_BASE);
1450
1451         if (!(in_sdram || warm_reset())) {
1452                 if (emif1_enabled)
1453                         emif_post_init_config(EMIF1_BASE);
1454                 if (emif2_enabled)
1455                         emif_post_init_config(EMIF2_BASE);
1456         }
1457
1458         /* for the shadow registers to take effect */
1459         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1460                 freq_update_core();
1461
1462         /* Do some testing after the init */
1463         if (!in_sdram) {
1464                 size_prog = omap_sdram_size();
1465                 size_prog = log_2_n_round_down(size_prog);
1466                 size_prog = (1 << size_prog);
1467
1468                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1469                                                 size_prog);
1470                 /* Compare with the size programmed */
1471                 if (size_detect != size_prog) {
1472                         printf("SDRAM: identified size not same as expected"
1473                                 " size identified: %x expected: %x\n",
1474                                 size_detect,
1475                                 size_prog);
1476                 } else
1477                         debug("get_ram_size() successful");
1478         }
1479
1480         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1481             (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1482                 if (emif1_enabled)
1483                         do_bug0039_workaround(EMIF1_BASE);
1484                 if (emif2_enabled)
1485                         do_bug0039_workaround(EMIF2_BASE);
1486         }
1487
1488         debug("<<sdram_init()\n");
1489 }