5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
34 #include <linux/compiler.h>
36 static int emif1_enabled = -1, emif2_enabled = -1;
38 void set_lpmode_selfrefresh(u32 base)
40 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
43 reg = readl(&emif->emif_pwr_mgmt_ctrl);
44 reg &= ~EMIF_REG_LP_MODE_MASK;
45 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
46 reg &= ~EMIF_REG_SR_TIM_MASK;
47 writel(reg, &emif->emif_pwr_mgmt_ctrl);
49 /* dummy read for the new SR_TIM to be loaded */
50 readl(&emif->emif_pwr_mgmt_ctrl);
53 void force_emif_self_refresh()
55 set_lpmode_selfrefresh(EMIF1_BASE);
56 set_lpmode_selfrefresh(EMIF2_BASE);
59 inline u32 emif_num(u32 base)
61 if (base == EMIF1_BASE)
63 else if (base == EMIF2_BASE)
70 * Get SDRAM type connected to EMIF.
71 * Assuming similar SDRAM parts are connected to both EMIF's
72 * which is typically the case. So it is sufficient to get
73 * SDRAM type from EMIF1.
77 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
79 return (readl(&emif->emif_sdram_config) &
80 EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
83 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
86 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
88 mr_addr |= cs << EMIF_REG_CS_SHIFT;
89 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
90 if (omap_revision() == OMAP4430_ES2_0)
91 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
93 mr = readl(&emif->emif_lpddr2_mode_reg_data);
94 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
96 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
97 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
98 ((mr & 0xff000000) >> 24) == (mr & 0xff))
104 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
106 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
108 mr_addr |= cs << EMIF_REG_CS_SHIFT;
109 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
110 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
113 void emif_reset_phy(u32 base)
115 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
118 iodft = readl(&emif->emif_iodft_tlgc);
119 iodft |= EMIF_REG_RESET_PHY_MASK;
120 writel(iodft, &emif->emif_iodft_tlgc);
123 static void do_lpddr2_init(u32 base, u32 cs)
126 const struct lpddr2_mr_regs *mr_regs;
128 get_lpddr2_mr_regs(&mr_regs);
129 /* Wait till device auto initialization is complete */
130 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
132 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
135 * Enough loops assuming a maximum of 2GHz
140 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
141 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
144 * Enable refresh along with writing MR2
145 * Encoding of RL in MR2 is (RL - 2)
147 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
148 set_mr(base, cs, mr_addr, mr_regs->mr2);
150 if (mr_regs->mr3 > 0)
151 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
154 static void lpddr2_init(u32 base, const struct emif_regs *regs)
156 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
159 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
162 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
163 * when EMIF_SDRAM_CONFIG register is written
165 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
168 * Set the SDRAM_CONFIG and PHY_CTRL for the
169 * un-locked frequency & default RL
171 writel(regs->sdram_config_init, &emif->emif_sdram_config);
172 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
174 do_ext_phy_settings(base, regs);
176 do_lpddr2_init(base, CS0);
177 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
178 do_lpddr2_init(base, CS1);
180 writel(regs->sdram_config, &emif->emif_sdram_config);
181 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
183 /* Enable refresh now */
184 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
188 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
192 void emif_update_timings(u32 base, const struct emif_regs *regs)
194 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
196 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
197 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
198 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
199 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
200 if (omap_revision() == OMAP4430_ES1_0) {
201 /* ES1 bug EMIF should be in force idle during freq_update */
202 writel(0, &emif->emif_pwr_mgmt_ctrl);
204 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
205 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
207 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
208 writel(regs->zq_config, &emif->emif_zq_config);
209 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
210 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
212 if (omap_revision() >= OMAP5430_ES1_0) {
213 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
214 &emif->emif_l3_config);
215 } else if (omap_revision() >= OMAP4460_ES1_0) {
216 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
217 &emif->emif_l3_config);
219 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
220 &emif->emif_l3_config);
224 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
226 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
228 /* keep sdram in self-refresh */
229 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
230 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
234 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
235 * Invert clock adds an additional half cycle delay on the command
236 * interface. The additional half cycle, is usually meant to enable
237 * leveling in the situation that DQS is later than CK on the board.It
238 * also helps provide some additional margin for leveling.
240 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
241 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
244 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
245 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
247 /* Launch Full leveling */
248 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
250 /* Wait till full leveling is complete */
251 readl(&emif->emif_rd_wr_lvl_ctl);
254 /* Read data eye leveling no of samples */
255 config_data_eye_leveling_samples(base);
257 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
258 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
261 /* Launch Incremental leveling */
262 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
266 static void ddr3_init(u32 base, const struct emif_regs *regs)
268 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
271 * Set SDRAM_CONFIG and PHY control registers to locked frequency
272 * and RL =7. As the default values of the Mode Registers are not
273 * defined, contents of mode Registers must be fully initialized.
274 * H/W takes care of this initialization
276 writel(regs->sdram_config_init, &emif->emif_sdram_config);
278 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
280 /* Update timing registers */
281 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
282 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
283 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
285 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
286 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
288 do_ext_phy_settings(base, regs);
290 /* enable leveling */
291 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
293 ddr3_leveling(base, regs);
296 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
297 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
300 * Organization and refresh requirements for LPDDR2 devices of different
301 * types and densities. Derived from JESD209-2 section 2.4
303 const struct lpddr2_addressing addressing_table[] = {
304 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
305 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
306 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
307 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
308 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
309 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
310 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
311 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
312 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
313 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
314 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
317 static const u32 lpddr2_density_2_size_in_mbytes[] = {
331 * Calculate the period of DDR clock from frequency value and set the
332 * denominator and numerator in global variables for easy access later
334 static void set_ddr_clk_period(u32 freq)
338 * period_in_ns = 10^9/freq
342 cancel_out(T_num, T_den, 200);
347 * Convert time in nano seconds to number of cycles of DDR clock
349 static inline u32 ns_2_cycles(u32 ns)
351 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
355 * ns_2_cycles with the difference that the time passed is 2 times the actual
356 * value(to avoid fractions). The cycles returned is for the original value of
357 * the timing parameter
359 static inline u32 ns_x2_2_cycles(u32 ns)
361 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
365 * Find addressing table index based on the device's type(S2 or S4) and
368 s8 addressing_table_index(u8 type, u8 density, u8 width)
371 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
375 * Look at the way ADDR_TABLE_INDEX* values have been defined
376 * in emif.h compared to LPDDR2_DENSITY_* values
377 * The table is layed out in the increasing order of density
378 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
381 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
382 index = ADDR_TABLE_INDEX1GS2;
383 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
384 index = ADDR_TABLE_INDEX2GS2;
388 debug("emif: addressing table index %d\n", index);
394 * Find the the right timing table from the array of timing
395 * tables of the device using DDR clock frequency
397 static const struct lpddr2_ac_timings *get_timings_table(const struct
398 lpddr2_ac_timings const *const *device_timings,
401 u32 i, temp, freq_nearest;
402 const struct lpddr2_ac_timings *timings = 0;
404 emif_assert(freq <= MAX_LPDDR2_FREQ);
405 emif_assert(device_timings);
408 * Start with the maximum allowed frequency - that is always safe
410 freq_nearest = MAX_LPDDR2_FREQ;
412 * Find the timings table that has the max frequency value:
413 * i. Above or equal to the DDR frequency - safe
414 * ii. The lowest that satisfies condition (i) - optimal
416 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
417 temp = device_timings[i]->max_freq;
418 if ((temp >= freq) && (temp <= freq_nearest)) {
420 timings = device_timings[i];
423 debug("emif: timings table: %d\n", freq_nearest);
428 * Finds the value of emif_sdram_config_reg
429 * All parameters are programmed based on the device on CS0.
430 * If there is a device on CS1, it will be same as that on CS0 or
431 * it will be NVM. We don't support NVM yet.
432 * If cs1_device pointer is NULL it is assumed that there is no device
435 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
436 const struct lpddr2_device_details *cs1_device,
437 const struct lpddr2_addressing *addressing,
442 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
443 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
444 EMIF_REG_IBANK_POS_SHIFT;
446 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
448 config_reg |= RL << EMIF_REG_CL_SHIFT;
450 config_reg |= addressing->row_sz[cs0_device->io_width] <<
451 EMIF_REG_ROWSIZE_SHIFT;
453 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
455 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
456 EMIF_REG_EBANK_SHIFT;
458 config_reg |= addressing->col_sz[cs0_device->io_width] <<
459 EMIF_REG_PAGESIZE_SHIFT;
464 static u32 get_sdram_ref_ctrl(u32 freq,
465 const struct lpddr2_addressing *addressing)
467 u32 ref_ctrl = 0, val = 0, freq_khz;
468 freq_khz = freq / 1000;
470 * refresh rate to be set is 'tREFI * freq in MHz
471 * division by 10000 to account for khz and x10 in t_REFI_us_x10
473 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
474 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
479 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
480 const struct lpddr2_min_tck *min_tck,
481 const struct lpddr2_addressing *addressing)
483 u32 tim1 = 0, val = 0;
484 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
485 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
487 if (addressing->num_banks == BANKS8)
488 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
491 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
493 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
495 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
496 tim1 |= val << EMIF_REG_T_RC_SHIFT;
498 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
499 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
501 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
502 tim1 |= val << EMIF_REG_T_WR_SHIFT;
504 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
505 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
507 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
508 tim1 |= val << EMIF_REG_T_RP_SHIFT;
513 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
514 const struct lpddr2_min_tck *min_tck)
516 u32 tim2 = 0, val = 0;
517 val = max(min_tck->tCKE, timings->tCKE) - 1;
518 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
520 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
521 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
524 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
527 val = ns_2_cycles(timings->tXSR) - 1;
528 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
529 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
531 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
532 tim2 |= val << EMIF_REG_T_XP_SHIFT;
537 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
538 const struct lpddr2_min_tck *min_tck,
539 const struct lpddr2_addressing *addressing)
541 u32 tim3 = 0, val = 0;
542 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
543 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
545 val = ns_2_cycles(timings->tRFCab) - 1;
546 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
548 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
549 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
551 val = ns_2_cycles(timings->tZQCS) - 1;
552 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
554 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
555 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
560 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
561 const struct lpddr2_addressing *addressing,
567 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
568 addressing->t_REFI_us_x10;
571 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
572 addressing->t_REFI_us_x10;
573 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
575 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
577 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
579 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
582 * Assuming that two chipselects have a single calibration resistor
583 * If there are indeed two calibration resistors, then this flag should
584 * be enabled to take advantage of dual calibration feature.
585 * This data should ideally come from board files. But considering
586 * that none of the boards today have calibration resistors per CS,
587 * it would be an unnecessary overhead.
589 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
591 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
593 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
598 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
599 const struct lpddr2_addressing *addressing,
602 u32 alert = 0, interval;
604 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
607 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
609 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
611 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
613 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
615 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
617 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
622 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
624 u32 idle = 0, val = 0;
626 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
628 /*Maximum value in normal conditions - suggested by hw team */
630 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
632 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
637 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
639 u32 phy = 0, val = 0;
641 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
643 if (freq <= 100000000)
644 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
645 else if (freq <= 200000000)
646 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
648 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
649 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
651 /* Other fields are constant magic values. Hardcode them together */
652 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
653 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
658 static u32 get_emif_mem_size(u32 base)
660 u32 size_mbytes = 0, temp;
661 struct emif_device_details dev_details;
662 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
663 u32 emif_nr = emif_num(base);
665 emif_reset_phy(base);
666 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
668 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
670 emif_reset_phy(base);
672 if (dev_details.cs0_device_details) {
673 temp = dev_details.cs0_device_details->density;
674 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
677 if (dev_details.cs1_device_details) {
678 temp = dev_details.cs1_device_details->density;
679 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
681 /* convert to bytes */
682 return size_mbytes << 20;
685 /* Gets the encoding corresponding to a given DMM section size */
686 u32 get_dmm_section_size_map(u32 section_size)
689 * Section size mapping:
690 * 0x0: 16-MiB section
691 * 0x1: 32-MiB section
692 * 0x2: 64-MiB section
693 * 0x3: 128-MiB section
694 * 0x4: 256-MiB section
695 * 0x5: 512-MiB section
699 section_size >>= 24; /* divide by 16 MB */
700 return log_2_n_round_down(section_size);
703 static void emif_calculate_regs(
704 const struct emif_device_details *emif_dev_details,
705 u32 freq, struct emif_regs *regs)
708 const struct lpddr2_addressing *addressing;
709 const struct lpddr2_ac_timings *timings;
710 const struct lpddr2_min_tck *min_tck;
711 const struct lpddr2_device_details *cs0_dev_details =
712 emif_dev_details->cs0_device_details;
713 const struct lpddr2_device_details *cs1_dev_details =
714 emif_dev_details->cs1_device_details;
715 const struct lpddr2_device_timings *cs0_dev_timings =
716 emif_dev_details->cs0_device_timings;
718 emif_assert(emif_dev_details);
721 * You can not have a device on CS1 without one on CS0
722 * So configuring EMIF without a device on CS0 doesn't
725 emif_assert(cs0_dev_details);
726 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
728 * If there is a device on CS1 it should be same type as CS0
729 * (or NVM. But NVM is not supported in this driver yet)
731 emif_assert((cs1_dev_details == NULL) ||
732 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
733 (cs0_dev_details->type == cs1_dev_details->type));
734 emif_assert(freq <= MAX_LPDDR2_FREQ);
736 set_ddr_clk_period(freq);
739 * The device on CS0 is used for all timing calculations
740 * There is only one set of registers for timings per EMIF. So, if the
741 * second CS(CS1) has a device, it should have the same timings as the
744 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
745 emif_assert(timings);
746 min_tck = cs0_dev_timings->min_tck;
748 temp = addressing_table_index(cs0_dev_details->type,
749 cs0_dev_details->density,
750 cs0_dev_details->io_width);
752 emif_assert((temp >= 0));
753 addressing = &(addressing_table[temp]);
754 emif_assert(addressing);
756 sys_freq = get_sys_clk_freq();
758 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
760 addressing, RL_BOOT);
762 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
764 addressing, RL_FINAL);
766 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
768 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
770 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
772 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
774 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
776 regs->temp_alert_config =
777 get_temp_alert_config(cs1_dev_details, addressing, 0);
779 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
780 LPDDR2_VOLTAGE_STABLE);
782 regs->emif_ddr_phy_ctlr_1_init =
783 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
785 regs->emif_ddr_phy_ctlr_1 =
786 get_ddr_phy_ctrl_1(freq, RL_FINAL);
790 print_timing_reg(regs->sdram_config_init);
791 print_timing_reg(regs->sdram_config);
792 print_timing_reg(regs->ref_ctrl);
793 print_timing_reg(regs->sdram_tim1);
794 print_timing_reg(regs->sdram_tim2);
795 print_timing_reg(regs->sdram_tim3);
796 print_timing_reg(regs->read_idle_ctrl);
797 print_timing_reg(regs->temp_alert_config);
798 print_timing_reg(regs->zq_config);
799 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
800 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
802 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
804 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
805 const char *get_lpddr2_type(u8 type_id)
817 const char *get_lpddr2_io_width(u8 width_id)
820 case LPDDR2_IO_WIDTH_8:
822 case LPDDR2_IO_WIDTH_16:
824 case LPDDR2_IO_WIDTH_32:
831 const char *get_lpddr2_manufacturer(u32 manufacturer)
833 switch (manufacturer) {
834 case LPDDR2_MANUFACTURER_SAMSUNG:
836 case LPDDR2_MANUFACTURER_QIMONDA:
838 case LPDDR2_MANUFACTURER_ELPIDA:
840 case LPDDR2_MANUFACTURER_ETRON:
842 case LPDDR2_MANUFACTURER_NANYA:
844 case LPDDR2_MANUFACTURER_HYNIX:
846 case LPDDR2_MANUFACTURER_MOSEL:
848 case LPDDR2_MANUFACTURER_WINBOND:
850 case LPDDR2_MANUFACTURER_ESMT:
852 case LPDDR2_MANUFACTURER_SPANSION:
854 case LPDDR2_MANUFACTURER_SST:
856 case LPDDR2_MANUFACTURER_ZMOS:
858 case LPDDR2_MANUFACTURER_INTEL:
860 case LPDDR2_MANUFACTURER_NUMONYX:
862 case LPDDR2_MANUFACTURER_MICRON:
869 static void display_sdram_details(u32 emif_nr, u32 cs,
870 struct lpddr2_device_details *device)
873 const char *type_str;
874 char density_str[10];
877 debug("EMIF%d CS%d\t", emif_nr, cs);
884 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
885 type_str = get_lpddr2_type(device->type);
887 density = lpddr2_density_2_size_in_mbytes[device->density];
888 if ((density / 1024 * 1024) == density) {
890 sprintf(density_str, "%d GB", density);
892 sprintf(density_str, "%d MB", density);
893 if (mfg_str && type_str)
894 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
897 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
898 struct lpddr2_device_details *lpddr2_device)
902 mr = get_mr(base, cs, LPDDR2_MR0);
904 /* Mode register value bigger than 8 bit */
908 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
913 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
916 /* DNV supported - But DNV is only supported for NVM */
920 mr = get_mr(base, cs, LPDDR2_MR4);
922 /* Mode register value bigger than 8 bit */
926 mr = get_mr(base, cs, LPDDR2_MR5);
928 /* Mode register value bigger than 8 bit */
932 if (!get_lpddr2_manufacturer(mr)) {
933 /* Manufacturer not identified */
936 lpddr2_device->manufacturer = mr;
938 mr = get_mr(base, cs, LPDDR2_MR6);
940 /* Mode register value bigger than 8 bit */
944 mr = get_mr(base, cs, LPDDR2_MR7);
946 /* Mode register value bigger than 8 bit */
950 mr = get_mr(base, cs, LPDDR2_MR8);
952 /* Mode register value bigger than 8 bit */
956 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
957 if (!get_lpddr2_type(temp)) {
961 lpddr2_device->type = temp;
963 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
964 if (temp > LPDDR2_DENSITY_32Gb) {
965 /* Density not supported */
968 lpddr2_device->density = temp;
970 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
971 if (!get_lpddr2_io_width(temp)) {
972 /* IO width unsupported value */
975 lpddr2_device->io_width = temp;
978 * If all the above tests pass we should
979 * have a device on this chip-select
984 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
985 struct lpddr2_device_details *lpddr2_dev_details)
988 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
990 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
992 if (!lpddr2_dev_details)
995 /* Do the minimum init for mode register accesses */
996 if (!(running_from_sdram() || warm_reset())) {
997 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
998 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1001 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1004 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1006 return lpddr2_dev_details;
1008 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1010 static void do_sdram_init(u32 base)
1012 const struct emif_regs *regs;
1013 u32 in_sdram, emif_nr;
1015 debug(">>do_sdram_init() %x\n", base);
1017 in_sdram = running_from_sdram();
1018 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1020 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1021 emif_get_reg_dump(emif_nr, ®s);
1023 debug("EMIF: reg dump not provided\n");
1028 * The user has not provided the register values. We need to
1029 * calculate it based on the timings and the DDR frequency
1031 struct emif_device_details dev_details;
1032 struct emif_regs calculated_regs;
1035 * Get device details:
1036 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1037 * - Obtained from user otherwise
1039 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1040 emif_reset_phy(base);
1041 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1043 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1045 emif_reset_phy(base);
1047 /* Return if no devices on this EMIF */
1048 if (!dev_details.cs0_device_details &&
1049 !dev_details.cs1_device_details) {
1054 * Get device timings:
1055 * - Default timings specified by JESD209-2 if
1056 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1057 * - Obtained from user otherwise
1059 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1060 &dev_details.cs1_device_timings);
1062 /* Calculate the register values */
1063 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1064 regs = &calculated_regs;
1065 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1068 * Initializing the LPDDR2 device can not happen from SDRAM.
1069 * Changing the timing registers in EMIF can happen(going from one
1072 if (!(in_sdram || warm_reset())) {
1073 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1074 lpddr2_init(base, regs);
1076 ddr3_init(base, regs);
1078 if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1079 set_lpmode_selfrefresh(base);
1080 emif_reset_phy(base);
1081 ddr3_leveling(base, regs);
1084 /* Write to the shadow registers */
1085 emif_update_timings(base, regs);
1087 debug("<<do_sdram_init() %x\n", base);
1090 void emif_post_init_config(u32 base)
1092 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1093 u32 omap_rev = omap_revision();
1095 /* reset phy on ES2.0 */
1096 if (omap_rev == OMAP4430_ES2_0)
1097 emif_reset_phy(base);
1099 /* Put EMIF back in smart idle on ES1.0 */
1100 if (omap_rev == OMAP4430_ES1_0)
1101 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1104 void dmm_init(u32 base)
1106 const struct dmm_lisa_map_regs *lisa_map_regs;
1107 u32 i, section, valid;
1109 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1110 emif_get_dmm_regs(&lisa_map_regs);
1112 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1113 u32 section_cnt, sys_addr;
1114 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1118 sys_addr = CONFIG_SYS_SDRAM_BASE;
1119 emif1_size = get_emif_mem_size(EMIF1_BASE);
1120 emif2_size = get_emif_mem_size(EMIF2_BASE);
1121 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1123 if (!emif1_size && !emif2_size)
1126 /* symmetric interleaved section */
1127 if (emif1_size && emif2_size) {
1128 mapped_size = min(emif1_size, emif2_size);
1129 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1130 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1132 section_map |= (sys_addr >> 24) <<
1133 EMIF_SYS_ADDR_SHIFT;
1134 section_map |= get_dmm_section_size_map(mapped_size * 2)
1135 << EMIF_SYS_SIZE_SHIFT;
1136 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1137 emif1_size -= mapped_size;
1138 emif2_size -= mapped_size;
1139 sys_addr += (mapped_size * 2);
1144 * Single EMIF section(we can have a maximum of 1 single EMIF
1145 * section- either EMIF1 or EMIF2 or none, but not both)
1148 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1149 section_map |= get_dmm_section_size_map(emif1_size)
1150 << EMIF_SYS_SIZE_SHIFT;
1152 section_map |= (mapped_size >> 24) <<
1153 EMIF_SDRC_ADDR_SHIFT;
1155 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1159 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1160 section_map |= get_dmm_section_size_map(emif2_size) <<
1161 EMIF_SYS_SIZE_SHIFT;
1163 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1165 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1169 if (section_cnt == 2) {
1170 /* Only 1 section - either symmetric or single EMIF */
1171 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1172 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1173 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1175 /* 2 sections - 1 symmetric, 1 single EMIF */
1176 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1177 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1180 /* TRAP for invalid TILER mappings in section 0 */
1181 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1183 lisa_map_regs = &lis_map_regs_calculated;
1185 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1186 (struct dmm_lisa_map_regs *)base;
1188 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1189 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1190 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1191 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1193 writel(lisa_map_regs->dmm_lisa_map_3,
1194 &hw_lisa_map_regs->dmm_lisa_map_3);
1195 writel(lisa_map_regs->dmm_lisa_map_2,
1196 &hw_lisa_map_regs->dmm_lisa_map_2);
1197 writel(lisa_map_regs->dmm_lisa_map_1,
1198 &hw_lisa_map_regs->dmm_lisa_map_1);
1199 writel(lisa_map_regs->dmm_lisa_map_0,
1200 &hw_lisa_map_regs->dmm_lisa_map_0);
1202 if (lisa_map_regs->is_ma_present) {
1204 (struct dmm_lisa_map_regs *)MA_BASE;
1206 writel(lisa_map_regs->dmm_lisa_map_3,
1207 &hw_lisa_map_regs->dmm_lisa_map_3);
1208 writel(lisa_map_regs->dmm_lisa_map_2,
1209 &hw_lisa_map_regs->dmm_lisa_map_2);
1210 writel(lisa_map_regs->dmm_lisa_map_1,
1211 &hw_lisa_map_regs->dmm_lisa_map_1);
1212 writel(lisa_map_regs->dmm_lisa_map_0,
1213 &hw_lisa_map_regs->dmm_lisa_map_0);
1217 * EMIF should be configured only when
1218 * memory is mapped on it. Using emif1_enabled
1219 * and emif2_enabled variables for this.
1223 for (i = 0; i < 4; i++) {
1224 section = __raw_readl(DMM_BASE + i*4);
1225 valid = (section & EMIF_SDRC_MAP_MASK) >>
1226 (EMIF_SDRC_MAP_SHIFT);
1231 } else if (valid == 1) {
1233 } else if (valid == 2) {
1241 * SDRAM initialization:
1242 * SDRAM initialization has two parts:
1243 * 1. Configuring the SDRAM device
1244 * 2. Update the AC timings related parameters in the EMIF module
1245 * (1) should be done only once and should not be done while we are
1246 * running from SDRAM.
1247 * (2) can and should be done more than once if OPP changes.
1248 * Particularly, this may be needed when we boot without SPL and
1249 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1250 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1251 * the frequency. So,
1252 * Doing (1) and (2) makes sense - first time initialization
1253 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1254 * Doing (1) and not (2) doen't make sense
1255 * See do_sdram_init() for the details
1257 void sdram_init(void)
1259 u32 in_sdram, size_prog, size_detect;
1260 u32 sdram_type = emif_sdram_type();
1262 debug(">>sdram_init()\n");
1264 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1267 in_sdram = running_from_sdram();
1268 debug("in_sdram = %d\n", in_sdram);
1271 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1272 bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1273 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1274 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1281 do_sdram_init(EMIF1_BASE);
1284 do_sdram_init(EMIF2_BASE);
1286 if (!(in_sdram || warm_reset())) {
1288 emif_post_init_config(EMIF1_BASE);
1290 emif_post_init_config(EMIF2_BASE);
1293 /* for the shadow registers to take effect */
1294 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1297 /* Do some testing after the init */
1299 size_prog = omap_sdram_size();
1300 size_prog = log_2_n_round_down(size_prog);
1301 size_prog = (1 << size_prog);
1303 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1305 /* Compare with the size programmed */
1306 if (size_detect != size_prog) {
1307 printf("SDRAM: identified size not same as expected"
1308 " size identified: %x expected: %x\n",
1312 debug("get_ram_size() successful");
1315 debug("<<sdram_init()\n");