5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/omap_common.h>
17 #include <asm/utils.h>
18 #include <linux/compiler.h>
20 static int emif1_enabled = -1, emif2_enabled = -1;
22 void set_lpmode_selfrefresh(u32 base)
24 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
27 reg = readl(&emif->emif_pwr_mgmt_ctrl);
28 reg &= ~EMIF_REG_LP_MODE_MASK;
29 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
30 reg &= ~EMIF_REG_SR_TIM_MASK;
31 writel(reg, &emif->emif_pwr_mgmt_ctrl);
33 /* dummy read for the new SR_TIM to be loaded */
34 readl(&emif->emif_pwr_mgmt_ctrl);
37 void force_emif_self_refresh()
39 set_lpmode_selfrefresh(EMIF1_BASE);
40 set_lpmode_selfrefresh(EMIF2_BASE);
43 inline u32 emif_num(u32 base)
45 if (base == EMIF1_BASE)
47 else if (base == EMIF2_BASE)
53 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
56 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
58 mr_addr |= cs << EMIF_REG_CS_SHIFT;
59 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
60 if (omap_revision() == OMAP4430_ES2_0)
61 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
63 mr = readl(&emif->emif_lpddr2_mode_reg_data);
64 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
66 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
67 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
68 ((mr & 0xff000000) >> 24) == (mr & 0xff))
74 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
76 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
78 mr_addr |= cs << EMIF_REG_CS_SHIFT;
79 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
80 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
83 void emif_reset_phy(u32 base)
85 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
88 iodft = readl(&emif->emif_iodft_tlgc);
89 iodft |= EMIF_REG_RESET_PHY_MASK;
90 writel(iodft, &emif->emif_iodft_tlgc);
93 static void do_lpddr2_init(u32 base, u32 cs)
96 const struct lpddr2_mr_regs *mr_regs;
98 get_lpddr2_mr_regs(&mr_regs);
99 /* Wait till device auto initialization is complete */
100 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
102 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
105 * Enough loops assuming a maximum of 2GHz
110 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
111 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
114 * Enable refresh along with writing MR2
115 * Encoding of RL in MR2 is (RL - 2)
117 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
118 set_mr(base, cs, mr_addr, mr_regs->mr2);
120 if (mr_regs->mr3 > 0)
121 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
124 static void lpddr2_init(u32 base, const struct emif_regs *regs)
126 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
129 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
132 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
133 * when EMIF_SDRAM_CONFIG register is written
135 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
138 * Set the SDRAM_CONFIG and PHY_CTRL for the
139 * un-locked frequency & default RL
141 writel(regs->sdram_config_init, &emif->emif_sdram_config);
142 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
144 do_ext_phy_settings(base, regs);
146 do_lpddr2_init(base, CS0);
147 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
148 do_lpddr2_init(base, CS1);
150 writel(regs->sdram_config, &emif->emif_sdram_config);
151 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
153 /* Enable refresh now */
154 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
158 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
162 void emif_update_timings(u32 base, const struct emif_regs *regs)
164 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
166 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
167 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
168 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
169 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
170 if (omap_revision() == OMAP4430_ES1_0) {
171 /* ES1 bug EMIF should be in force idle during freq_update */
172 writel(0, &emif->emif_pwr_mgmt_ctrl);
174 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
175 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
177 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
178 writel(regs->zq_config, &emif->emif_zq_config);
179 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
180 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
182 if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
183 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
184 &emif->emif_l3_config);
185 } else if (omap_revision() >= OMAP4460_ES1_0) {
186 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
187 &emif->emif_l3_config);
189 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
190 &emif->emif_l3_config);
194 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
196 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
198 /* keep sdram in self-refresh */
199 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
200 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
204 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
205 * Invert clock adds an additional half cycle delay on the
206 * command interface. The additional half cycle, is usually
207 * meant to enable leveling in the situation that DQS is later
208 * than CK on the board.It also helps provide some additional
209 * margin for leveling.
211 writel(regs->emif_ddr_phy_ctlr_1,
212 &emif->emif_ddr_phy_ctrl_1);
214 writel(regs->emif_ddr_phy_ctlr_1,
215 &emif->emif_ddr_phy_ctrl_1_shdw);
218 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
219 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
221 /* Launch Full leveling */
222 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
224 /* Wait till full leveling is complete */
225 readl(&emif->emif_rd_wr_lvl_ctl);
228 /* Read data eye leveling no of samples */
229 config_data_eye_leveling_samples(base);
232 * Launch 8 incremental WR_LVL- to compensate for
235 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
236 &emif->emif_rd_wr_lvl_ctl);
240 /* Launch Incremental leveling */
241 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
245 static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
247 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
248 u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
251 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
253 /* Update PHY_REG_RDDQS_RATIO */
254 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
255 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
256 reg = readl(emif_phy_status++);
257 writel(reg, emif_ext_phy_ctrl_reg++);
258 writel(reg, emif_ext_phy_ctrl_reg++);
261 /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
262 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
263 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
264 reg = readl(emif_phy_status++);
265 writel(reg, emif_ext_phy_ctrl_reg++);
266 writel(reg, emif_ext_phy_ctrl_reg++);
269 /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
270 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
271 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
272 reg = readl(emif_phy_status++);
273 writel(reg, emif_ext_phy_ctrl_reg++);
274 writel(reg, emif_ext_phy_ctrl_reg++);
277 /* Disable Leveling */
278 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
279 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
280 writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
283 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
285 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
287 /* Clear Error Status */
288 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
289 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
290 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
292 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
293 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
294 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
296 /* Disable refreshed before leveling */
297 clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
298 EMIF_REG_INITREF_DIS_SHIFT);
300 /* Start Full leveling */
301 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
305 /* Check for leveling timeout */
306 if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
307 printf("Leveling timeout on EMIF%d\n", emif_num(base));
311 /* Enable refreshes after leveling */
312 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
314 debug("HW leveling success\n");
316 * Update slave ratios in EXT_PHY_CTRLx registers
317 * as per HW leveling output
319 update_hwleveling_output(base, regs);
322 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
324 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
327 emif_reset_phy(base);
328 do_ext_phy_settings(base, regs);
330 writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
331 &emif->emif_sdram_ref_ctrl);
332 /* Update timing registers */
333 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
334 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
335 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
337 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
338 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
339 writel(regs->zq_config, &emif->emif_zq_config);
340 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
341 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
342 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
344 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
345 writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
347 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
349 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
350 writel(regs->sdram_config_init, &emif->emif_sdram_config);
354 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
356 if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
357 dra7_ddr3_leveling(base, regs);
360 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
362 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
364 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
365 writel(regs->sdram_config_init, &emif->emif_sdram_config);
367 * Set SDRAM_CONFIG and PHY control registers to locked frequency
368 * and RL =7. As the default values of the Mode Registers are not
369 * defined, contents of mode Registers must be fully initialized.
370 * H/W takes care of this initialization
372 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
374 /* Update timing registers */
375 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
376 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
377 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
379 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
381 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
382 writel(regs->sdram_config_init, &emif->emif_sdram_config);
383 do_ext_phy_settings(base, regs);
385 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
386 omap5_ddr3_leveling(base, regs);
389 static void ddr3_init(u32 base, const struct emif_regs *regs)
392 omap5_ddr3_init(base, regs);
394 dra7_ddr3_init(base, regs);
397 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
398 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
401 * Organization and refresh requirements for LPDDR2 devices of different
402 * types and densities. Derived from JESD209-2 section 2.4
404 const struct lpddr2_addressing addressing_table[] = {
405 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
406 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
407 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
408 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
409 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
410 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
411 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
412 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
413 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
414 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
415 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
418 static const u32 lpddr2_density_2_size_in_mbytes[] = {
432 * Calculate the period of DDR clock from frequency value and set the
433 * denominator and numerator in global variables for easy access later
435 static void set_ddr_clk_period(u32 freq)
439 * period_in_ns = 10^9/freq
443 cancel_out(T_num, T_den, 200);
448 * Convert time in nano seconds to number of cycles of DDR clock
450 static inline u32 ns_2_cycles(u32 ns)
452 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
456 * ns_2_cycles with the difference that the time passed is 2 times the actual
457 * value(to avoid fractions). The cycles returned is for the original value of
458 * the timing parameter
460 static inline u32 ns_x2_2_cycles(u32 ns)
462 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
466 * Find addressing table index based on the device's type(S2 or S4) and
469 s8 addressing_table_index(u8 type, u8 density, u8 width)
472 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
476 * Look at the way ADDR_TABLE_INDEX* values have been defined
477 * in emif.h compared to LPDDR2_DENSITY_* values
478 * The table is layed out in the increasing order of density
479 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
482 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
483 index = ADDR_TABLE_INDEX1GS2;
484 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
485 index = ADDR_TABLE_INDEX2GS2;
489 debug("emif: addressing table index %d\n", index);
495 * Find the the right timing table from the array of timing
496 * tables of the device using DDR clock frequency
498 static const struct lpddr2_ac_timings *get_timings_table(const struct
499 lpddr2_ac_timings const *const *device_timings,
502 u32 i, temp, freq_nearest;
503 const struct lpddr2_ac_timings *timings = 0;
505 emif_assert(freq <= MAX_LPDDR2_FREQ);
506 emif_assert(device_timings);
509 * Start with the maximum allowed frequency - that is always safe
511 freq_nearest = MAX_LPDDR2_FREQ;
513 * Find the timings table that has the max frequency value:
514 * i. Above or equal to the DDR frequency - safe
515 * ii. The lowest that satisfies condition (i) - optimal
517 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
518 temp = device_timings[i]->max_freq;
519 if ((temp >= freq) && (temp <= freq_nearest)) {
521 timings = device_timings[i];
524 debug("emif: timings table: %d\n", freq_nearest);
529 * Finds the value of emif_sdram_config_reg
530 * All parameters are programmed based on the device on CS0.
531 * If there is a device on CS1, it will be same as that on CS0 or
532 * it will be NVM. We don't support NVM yet.
533 * If cs1_device pointer is NULL it is assumed that there is no device
536 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
537 const struct lpddr2_device_details *cs1_device,
538 const struct lpddr2_addressing *addressing,
543 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
544 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
545 EMIF_REG_IBANK_POS_SHIFT;
547 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
549 config_reg |= RL << EMIF_REG_CL_SHIFT;
551 config_reg |= addressing->row_sz[cs0_device->io_width] <<
552 EMIF_REG_ROWSIZE_SHIFT;
554 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
556 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
557 EMIF_REG_EBANK_SHIFT;
559 config_reg |= addressing->col_sz[cs0_device->io_width] <<
560 EMIF_REG_PAGESIZE_SHIFT;
565 static u32 get_sdram_ref_ctrl(u32 freq,
566 const struct lpddr2_addressing *addressing)
568 u32 ref_ctrl = 0, val = 0, freq_khz;
569 freq_khz = freq / 1000;
571 * refresh rate to be set is 'tREFI * freq in MHz
572 * division by 10000 to account for khz and x10 in t_REFI_us_x10
574 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
575 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
580 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
581 const struct lpddr2_min_tck *min_tck,
582 const struct lpddr2_addressing *addressing)
584 u32 tim1 = 0, val = 0;
585 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
586 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
588 if (addressing->num_banks == BANKS8)
589 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
592 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
594 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
596 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
597 tim1 |= val << EMIF_REG_T_RC_SHIFT;
599 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
600 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
602 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
603 tim1 |= val << EMIF_REG_T_WR_SHIFT;
605 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
606 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
608 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
609 tim1 |= val << EMIF_REG_T_RP_SHIFT;
614 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
615 const struct lpddr2_min_tck *min_tck)
617 u32 tim2 = 0, val = 0;
618 val = max(min_tck->tCKE, timings->tCKE) - 1;
619 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
621 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
622 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
625 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
628 val = ns_2_cycles(timings->tXSR) - 1;
629 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
630 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
632 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
633 tim2 |= val << EMIF_REG_T_XP_SHIFT;
638 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
639 const struct lpddr2_min_tck *min_tck,
640 const struct lpddr2_addressing *addressing)
642 u32 tim3 = 0, val = 0;
643 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
644 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
646 val = ns_2_cycles(timings->tRFCab) - 1;
647 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
649 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
650 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
652 val = ns_2_cycles(timings->tZQCS) - 1;
653 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
655 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
656 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
661 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
662 const struct lpddr2_addressing *addressing,
668 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
669 addressing->t_REFI_us_x10;
672 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
673 addressing->t_REFI_us_x10;
674 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
676 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
678 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
680 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
683 * Assuming that two chipselects have a single calibration resistor
684 * If there are indeed two calibration resistors, then this flag should
685 * be enabled to take advantage of dual calibration feature.
686 * This data should ideally come from board files. But considering
687 * that none of the boards today have calibration resistors per CS,
688 * it would be an unnecessary overhead.
690 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
692 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
694 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
699 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
700 const struct lpddr2_addressing *addressing,
703 u32 alert = 0, interval;
705 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
708 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
710 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
712 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
714 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
716 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
718 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
723 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
725 u32 idle = 0, val = 0;
727 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
729 /*Maximum value in normal conditions - suggested by hw team */
731 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
733 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
738 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
740 u32 phy = 0, val = 0;
742 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
744 if (freq <= 100000000)
745 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
746 else if (freq <= 200000000)
747 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
749 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
750 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
752 /* Other fields are constant magic values. Hardcode them together */
753 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
754 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
759 static u32 get_emif_mem_size(u32 base)
761 u32 size_mbytes = 0, temp;
762 struct emif_device_details dev_details;
763 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
764 u32 emif_nr = emif_num(base);
766 emif_reset_phy(base);
767 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
769 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
771 emif_reset_phy(base);
773 if (dev_details.cs0_device_details) {
774 temp = dev_details.cs0_device_details->density;
775 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
778 if (dev_details.cs1_device_details) {
779 temp = dev_details.cs1_device_details->density;
780 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
782 /* convert to bytes */
783 return size_mbytes << 20;
786 /* Gets the encoding corresponding to a given DMM section size */
787 u32 get_dmm_section_size_map(u32 section_size)
790 * Section size mapping:
791 * 0x0: 16-MiB section
792 * 0x1: 32-MiB section
793 * 0x2: 64-MiB section
794 * 0x3: 128-MiB section
795 * 0x4: 256-MiB section
796 * 0x5: 512-MiB section
800 section_size >>= 24; /* divide by 16 MB */
801 return log_2_n_round_down(section_size);
804 static void emif_calculate_regs(
805 const struct emif_device_details *emif_dev_details,
806 u32 freq, struct emif_regs *regs)
809 const struct lpddr2_addressing *addressing;
810 const struct lpddr2_ac_timings *timings;
811 const struct lpddr2_min_tck *min_tck;
812 const struct lpddr2_device_details *cs0_dev_details =
813 emif_dev_details->cs0_device_details;
814 const struct lpddr2_device_details *cs1_dev_details =
815 emif_dev_details->cs1_device_details;
816 const struct lpddr2_device_timings *cs0_dev_timings =
817 emif_dev_details->cs0_device_timings;
819 emif_assert(emif_dev_details);
822 * You can not have a device on CS1 without one on CS0
823 * So configuring EMIF without a device on CS0 doesn't
826 emif_assert(cs0_dev_details);
827 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
829 * If there is a device on CS1 it should be same type as CS0
830 * (or NVM. But NVM is not supported in this driver yet)
832 emif_assert((cs1_dev_details == NULL) ||
833 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
834 (cs0_dev_details->type == cs1_dev_details->type));
835 emif_assert(freq <= MAX_LPDDR2_FREQ);
837 set_ddr_clk_period(freq);
840 * The device on CS0 is used for all timing calculations
841 * There is only one set of registers for timings per EMIF. So, if the
842 * second CS(CS1) has a device, it should have the same timings as the
845 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
846 emif_assert(timings);
847 min_tck = cs0_dev_timings->min_tck;
849 temp = addressing_table_index(cs0_dev_details->type,
850 cs0_dev_details->density,
851 cs0_dev_details->io_width);
853 emif_assert((temp >= 0));
854 addressing = &(addressing_table[temp]);
855 emif_assert(addressing);
857 sys_freq = get_sys_clk_freq();
859 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
861 addressing, RL_BOOT);
863 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
865 addressing, RL_FINAL);
867 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
869 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
871 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
873 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
875 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
877 regs->temp_alert_config =
878 get_temp_alert_config(cs1_dev_details, addressing, 0);
880 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
881 LPDDR2_VOLTAGE_STABLE);
883 regs->emif_ddr_phy_ctlr_1_init =
884 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
886 regs->emif_ddr_phy_ctlr_1 =
887 get_ddr_phy_ctrl_1(freq, RL_FINAL);
891 print_timing_reg(regs->sdram_config_init);
892 print_timing_reg(regs->sdram_config);
893 print_timing_reg(regs->ref_ctrl);
894 print_timing_reg(regs->sdram_tim1);
895 print_timing_reg(regs->sdram_tim2);
896 print_timing_reg(regs->sdram_tim3);
897 print_timing_reg(regs->read_idle_ctrl);
898 print_timing_reg(regs->temp_alert_config);
899 print_timing_reg(regs->zq_config);
900 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
901 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
903 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
905 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
906 const char *get_lpddr2_type(u8 type_id)
918 const char *get_lpddr2_io_width(u8 width_id)
921 case LPDDR2_IO_WIDTH_8:
923 case LPDDR2_IO_WIDTH_16:
925 case LPDDR2_IO_WIDTH_32:
932 const char *get_lpddr2_manufacturer(u32 manufacturer)
934 switch (manufacturer) {
935 case LPDDR2_MANUFACTURER_SAMSUNG:
937 case LPDDR2_MANUFACTURER_QIMONDA:
939 case LPDDR2_MANUFACTURER_ELPIDA:
941 case LPDDR2_MANUFACTURER_ETRON:
943 case LPDDR2_MANUFACTURER_NANYA:
945 case LPDDR2_MANUFACTURER_HYNIX:
947 case LPDDR2_MANUFACTURER_MOSEL:
949 case LPDDR2_MANUFACTURER_WINBOND:
951 case LPDDR2_MANUFACTURER_ESMT:
953 case LPDDR2_MANUFACTURER_SPANSION:
955 case LPDDR2_MANUFACTURER_SST:
957 case LPDDR2_MANUFACTURER_ZMOS:
959 case LPDDR2_MANUFACTURER_INTEL:
961 case LPDDR2_MANUFACTURER_NUMONYX:
963 case LPDDR2_MANUFACTURER_MICRON:
970 static void display_sdram_details(u32 emif_nr, u32 cs,
971 struct lpddr2_device_details *device)
974 const char *type_str;
975 char density_str[10];
978 debug("EMIF%d CS%d\t", emif_nr, cs);
985 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
986 type_str = get_lpddr2_type(device->type);
988 density = lpddr2_density_2_size_in_mbytes[device->density];
989 if ((density / 1024 * 1024) == density) {
991 sprintf(density_str, "%d GB", density);
993 sprintf(density_str, "%d MB", density);
994 if (mfg_str && type_str)
995 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
998 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
999 struct lpddr2_device_details *lpddr2_device)
1003 mr = get_mr(base, cs, LPDDR2_MR0);
1005 /* Mode register value bigger than 8 bit */
1009 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
1014 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
1017 /* DNV supported - But DNV is only supported for NVM */
1021 mr = get_mr(base, cs, LPDDR2_MR4);
1023 /* Mode register value bigger than 8 bit */
1027 mr = get_mr(base, cs, LPDDR2_MR5);
1029 /* Mode register value bigger than 8 bit */
1033 if (!get_lpddr2_manufacturer(mr)) {
1034 /* Manufacturer not identified */
1037 lpddr2_device->manufacturer = mr;
1039 mr = get_mr(base, cs, LPDDR2_MR6);
1041 /* Mode register value bigger than 8 bit */
1045 mr = get_mr(base, cs, LPDDR2_MR7);
1047 /* Mode register value bigger than 8 bit */
1051 mr = get_mr(base, cs, LPDDR2_MR8);
1053 /* Mode register value bigger than 8 bit */
1057 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1058 if (!get_lpddr2_type(temp)) {
1062 lpddr2_device->type = temp;
1064 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1065 if (temp > LPDDR2_DENSITY_32Gb) {
1066 /* Density not supported */
1069 lpddr2_device->density = temp;
1071 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1072 if (!get_lpddr2_io_width(temp)) {
1073 /* IO width unsupported value */
1076 lpddr2_device->io_width = temp;
1079 * If all the above tests pass we should
1080 * have a device on this chip-select
1085 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1086 struct lpddr2_device_details *lpddr2_dev_details)
1089 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1091 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1093 if (!lpddr2_dev_details)
1096 /* Do the minimum init for mode register accesses */
1097 if (!(running_from_sdram() || warm_reset())) {
1098 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1099 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1102 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1105 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1107 return lpddr2_dev_details;
1109 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1111 static void do_sdram_init(u32 base)
1113 const struct emif_regs *regs;
1114 u32 in_sdram, emif_nr;
1116 debug(">>do_sdram_init() %x\n", base);
1118 in_sdram = running_from_sdram();
1119 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1121 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1122 emif_get_reg_dump(emif_nr, ®s);
1124 debug("EMIF: reg dump not provided\n");
1129 * The user has not provided the register values. We need to
1130 * calculate it based on the timings and the DDR frequency
1132 struct emif_device_details dev_details;
1133 struct emif_regs calculated_regs;
1136 * Get device details:
1137 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1138 * - Obtained from user otherwise
1140 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1141 emif_reset_phy(base);
1142 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1144 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1146 emif_reset_phy(base);
1148 /* Return if no devices on this EMIF */
1149 if (!dev_details.cs0_device_details &&
1150 !dev_details.cs1_device_details) {
1155 * Get device timings:
1156 * - Default timings specified by JESD209-2 if
1157 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1158 * - Obtained from user otherwise
1160 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1161 &dev_details.cs1_device_timings);
1163 /* Calculate the register values */
1164 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1165 regs = &calculated_regs;
1166 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1169 * Initializing the LPDDR2 device can not happen from SDRAM.
1170 * Changing the timing registers in EMIF can happen(going from one
1173 if (!(in_sdram || warm_reset())) {
1174 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1175 lpddr2_init(base, regs);
1177 ddr3_init(base, regs);
1179 if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1180 set_lpmode_selfrefresh(base);
1181 emif_reset_phy(base);
1182 omap5_ddr3_leveling(base, regs);
1185 /* Write to the shadow registers */
1186 emif_update_timings(base, regs);
1188 debug("<<do_sdram_init() %x\n", base);
1191 void emif_post_init_config(u32 base)
1193 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1194 u32 omap_rev = omap_revision();
1196 /* reset phy on ES2.0 */
1197 if (omap_rev == OMAP4430_ES2_0)
1198 emif_reset_phy(base);
1200 /* Put EMIF back in smart idle on ES1.0 */
1201 if (omap_rev == OMAP4430_ES1_0)
1202 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1205 void dmm_init(u32 base)
1207 const struct dmm_lisa_map_regs *lisa_map_regs;
1208 u32 i, section, valid;
1210 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1211 emif_get_dmm_regs(&lisa_map_regs);
1213 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1214 u32 section_cnt, sys_addr;
1215 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1219 sys_addr = CONFIG_SYS_SDRAM_BASE;
1220 emif1_size = get_emif_mem_size(EMIF1_BASE);
1221 emif2_size = get_emif_mem_size(EMIF2_BASE);
1222 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1224 if (!emif1_size && !emif2_size)
1227 /* symmetric interleaved section */
1228 if (emif1_size && emif2_size) {
1229 mapped_size = min(emif1_size, emif2_size);
1230 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1231 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1233 section_map |= (sys_addr >> 24) <<
1234 EMIF_SYS_ADDR_SHIFT;
1235 section_map |= get_dmm_section_size_map(mapped_size * 2)
1236 << EMIF_SYS_SIZE_SHIFT;
1237 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1238 emif1_size -= mapped_size;
1239 emif2_size -= mapped_size;
1240 sys_addr += (mapped_size * 2);
1245 * Single EMIF section(we can have a maximum of 1 single EMIF
1246 * section- either EMIF1 or EMIF2 or none, but not both)
1249 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1250 section_map |= get_dmm_section_size_map(emif1_size)
1251 << EMIF_SYS_SIZE_SHIFT;
1253 section_map |= (mapped_size >> 24) <<
1254 EMIF_SDRC_ADDR_SHIFT;
1256 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1260 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1261 section_map |= get_dmm_section_size_map(emif2_size) <<
1262 EMIF_SYS_SIZE_SHIFT;
1264 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1266 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1270 if (section_cnt == 2) {
1271 /* Only 1 section - either symmetric or single EMIF */
1272 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1273 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1274 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1276 /* 2 sections - 1 symmetric, 1 single EMIF */
1277 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1278 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1281 /* TRAP for invalid TILER mappings in section 0 */
1282 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1284 if (omap_revision() >= OMAP4460_ES1_0)
1285 lis_map_regs_calculated.is_ma_present = 1;
1287 lisa_map_regs = &lis_map_regs_calculated;
1289 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1290 (struct dmm_lisa_map_regs *)base;
1292 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1293 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1294 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1295 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1297 writel(lisa_map_regs->dmm_lisa_map_3,
1298 &hw_lisa_map_regs->dmm_lisa_map_3);
1299 writel(lisa_map_regs->dmm_lisa_map_2,
1300 &hw_lisa_map_regs->dmm_lisa_map_2);
1301 writel(lisa_map_regs->dmm_lisa_map_1,
1302 &hw_lisa_map_regs->dmm_lisa_map_1);
1303 writel(lisa_map_regs->dmm_lisa_map_0,
1304 &hw_lisa_map_regs->dmm_lisa_map_0);
1306 if (lisa_map_regs->is_ma_present) {
1308 (struct dmm_lisa_map_regs *)MA_BASE;
1310 writel(lisa_map_regs->dmm_lisa_map_3,
1311 &hw_lisa_map_regs->dmm_lisa_map_3);
1312 writel(lisa_map_regs->dmm_lisa_map_2,
1313 &hw_lisa_map_regs->dmm_lisa_map_2);
1314 writel(lisa_map_regs->dmm_lisa_map_1,
1315 &hw_lisa_map_regs->dmm_lisa_map_1);
1316 writel(lisa_map_regs->dmm_lisa_map_0,
1317 &hw_lisa_map_regs->dmm_lisa_map_0);
1321 * EMIF should be configured only when
1322 * memory is mapped on it. Using emif1_enabled
1323 * and emif2_enabled variables for this.
1327 for (i = 0; i < 4; i++) {
1328 section = __raw_readl(DMM_BASE + i*4);
1329 valid = (section & EMIF_SDRC_MAP_MASK) >>
1330 (EMIF_SDRC_MAP_SHIFT);
1345 static void do_bug0039_workaround(u32 base)
1347 u32 val, i, clkctrl;
1348 struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1349 const struct read_write_regs *bug_00339_regs;
1351 u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1352 u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1357 bug_00339_regs = get_bug_regs(&iterations);
1359 /* Put EMIF in to idle */
1360 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1361 __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1363 /* Copy the phy status registers in to phy ctrl shadow registers */
1364 for (i = 0; i < iterations; i++) {
1365 val = __raw_readl(phy_status_base +
1366 bug_00339_regs[i].read_reg - 1);
1368 __raw_writel(val, phy_ctrl_base +
1369 ((bug_00339_regs[i].write_reg - 1) << 1));
1371 __raw_writel(val, phy_ctrl_base +
1372 (bug_00339_regs[i].write_reg << 1) - 1);
1375 /* Disable leveling */
1376 writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1378 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
1382 * SDRAM initialization:
1383 * SDRAM initialization has two parts:
1384 * 1. Configuring the SDRAM device
1385 * 2. Update the AC timings related parameters in the EMIF module
1386 * (1) should be done only once and should not be done while we are
1387 * running from SDRAM.
1388 * (2) can and should be done more than once if OPP changes.
1389 * Particularly, this may be needed when we boot without SPL and
1390 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1391 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1392 * the frequency. So,
1393 * Doing (1) and (2) makes sense - first time initialization
1394 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1395 * Doing (1) and not (2) doen't make sense
1396 * See do_sdram_init() for the details
1398 void sdram_init(void)
1400 u32 in_sdram, size_prog, size_detect;
1401 u32 sdram_type = emif_sdram_type();
1403 debug(">>sdram_init()\n");
1405 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1408 in_sdram = running_from_sdram();
1409 debug("in_sdram = %d\n", in_sdram);
1412 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1413 bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1414 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1415 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1422 do_sdram_init(EMIF1_BASE);
1425 do_sdram_init(EMIF2_BASE);
1427 if (!(in_sdram || warm_reset())) {
1429 emif_post_init_config(EMIF1_BASE);
1431 emif_post_init_config(EMIF2_BASE);
1434 /* for the shadow registers to take effect */
1435 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1438 /* Do some testing after the init */
1440 size_prog = omap_sdram_size();
1441 size_prog = log_2_n_round_down(size_prog);
1442 size_prog = (1 << size_prog);
1444 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1446 /* Compare with the size programmed */
1447 if (size_detect != size_prog) {
1448 printf("SDRAM: identified size not same as expected"
1449 " size identified: %x expected: %x\n",
1453 debug("get_ram_size() successful");
1456 if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1457 (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1459 do_bug0039_workaround(EMIF1_BASE);
1461 do_bug0039_workaround(EMIF2_BASE);
1464 debug("<<sdram_init()\n");