git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         set_lpmode_selfrefresh(EMIF2_BASE);
  41 }
  42
  43 inline u32 emif_num(u32 base)
  44 {
  45         if (base == EMIF1_BASE)
  46                 return 1;
  47         else if (base == EMIF2_BASE)
  48                 return 2;
  49         else
  50                 return 0;
  51 }
  52
  53 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  54 {
  55         u32 mr;
  56         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  57
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  60         if (omap_revision() == OMAP4430_ES2_0)
  61                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  62         else
  63                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  64         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  65               cs, mr_addr, mr);
  66         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  67             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  68             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  69                 return mr & 0xff;
  70         else
  71                 return mr;
  72 }
  73
  74 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  75 {
  76         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  77
  78         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  79         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  80         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  81 }
  82
  83 void emif_reset_phy(u32 base)
  84 {
  85         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  86         u32 iodft;
  87
  88         iodft = readl(&emif->emif_iodft_tlgc);
  89         iodft |= EMIF_REG_RESET_PHY_MASK;
  90         writel(iodft, &emif->emif_iodft_tlgc);
  91 }
  92
  93 static void do_lpddr2_init(u32 base, u32 cs)
  94 {
  95         u32 mr_addr;
  96         const struct lpddr2_mr_regs *mr_regs;
  97
  98         get_lpddr2_mr_regs(&mr_regs);
  99         /* Wait till device auto initialization is complete */
 100         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 101                 ;
 102         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 103         /*
 104          * tZQINIT = 1 us
 105          * Enough loops assuming a maximum of 2GHz
 106          */
 107
 108         sdelay(2000);
 109
 110         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 111         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 112
 113         /*
 114          * Enable refresh along with writing MR2
 115          * Encoding of RL in MR2 is (RL - 2)
 116          */
 117         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 118         set_mr(base, cs, mr_addr, mr_regs->mr2);
 119
 120         if (mr_regs->mr3 > 0)
 121                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 122 }
 123
 124 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 125 {
 126         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 127
 128         /* Not NVM */
 129         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 130
 131         /*
 132          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 133          * when EMIF_SDRAM_CONFIG register is written
 134          */
 135         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 136
 137         /*
 138          * Set the SDRAM_CONFIG and PHY_CTRL for the
 139          * un-locked frequency & default RL
 140          */
 141         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 142         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 143
 144         do_ext_phy_settings(base, regs);
 145
 146         do_lpddr2_init(base, CS0);
 147         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 148                 do_lpddr2_init(base, CS1);
 149
 150         writel(regs->sdram_config, &emif->emif_sdram_config);
 151         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 152
 153         /* Enable refresh now */
 154         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 155
 156         }
 157
 158 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 159 {
 160 }
 161
 162 void emif_update_timings(u32 base, const struct emif_regs *regs)
 163 {
 164         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 165
 166         if (!is_dra7xx())
 167                 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 168         else
 169                 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
 170
 171         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 172         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 173         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 174         if (omap_revision() == OMAP4430_ES1_0) {
 175                 /* ES1 bug EMIF should be in force idle during freq_update */
 176                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 177         } else {
 178                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 179                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 180         }
 181         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 182         writel(regs->zq_config, &emif->emif_zq_config);
 183         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 184         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 185
 186         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 187                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 188                         &emif->emif_l3_config);
 189         } else if (omap_revision() >= OMAP4460_ES1_0) {
 190                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 191                         &emif->emif_l3_config);
 192         } else {
 193                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 194                         &emif->emif_l3_config);
 195         }
 196 }
 197
 198 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 199 {
 200         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 201
 202         /* keep sdram in self-refresh */
 203         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 204                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 205         __udelay(130);
 206
 207         /*
 208          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 209          * Invert clock adds an additional half cycle delay on the
 210          * command interface.  The additional half cycle, is usually
 211          * meant to enable leveling in the situation that DQS is later
 212          * than CK on the board.It also helps provide some additional
 213          * margin for leveling.
 214          */
 215         writel(regs->emif_ddr_phy_ctlr_1,
 216                &emif->emif_ddr_phy_ctrl_1);
 217
 218         writel(regs->emif_ddr_phy_ctlr_1,
 219                &emif->emif_ddr_phy_ctrl_1_shdw);
 220         __udelay(130);
 221
 222         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 223                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 224
 225         /* Launch Full leveling */
 226         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 227
 228         /* Wait till full leveling is complete */
 229         readl(&emif->emif_rd_wr_lvl_ctl);
 230               __udelay(130);
 231
 232         /* Read data eye leveling no of samples */
 233         config_data_eye_leveling_samples(base);
 234
 235         /*
 236          * Launch 8 incremental WR_LVL- to compensate for
 237          * PHY limitation.
 238          */
 239         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 240                &emif->emif_rd_wr_lvl_ctl);
 241
 242         __udelay(130);
 243
 244         /* Launch Incremental leveling */
 245         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 246                __udelay(130);
 247 }
 248
 249 static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 250 {
 251         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 252         u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
 253         u32 reg, i;
 254
 255         emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
 256
 257         /* Update PHY_REG_RDDQS_RATIO */
 258         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
 259         for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
 260                 reg = readl(emif_phy_status++);
 261                 writel(reg, emif_ext_phy_ctrl_reg++);
 262                 writel(reg, emif_ext_phy_ctrl_reg++);
 263         }
 264
 265         /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
 266         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
 267         for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
 268                 reg = readl(emif_phy_status++);
 269                 writel(reg, emif_ext_phy_ctrl_reg++);
 270                 writel(reg, emif_ext_phy_ctrl_reg++);
 271         }
 272
 273         /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
 274         emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
 275         for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
 276                 reg = readl(emif_phy_status++);
 277                 writel(reg, emif_ext_phy_ctrl_reg++);
 278                 writel(reg, emif_ext_phy_ctrl_reg++);
 279         }
 280
 281         /* Disable Leveling */
 282         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 283         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 284         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 285 }
 286
 287 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 288 {
 289         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 290
 291         /* Clear Error Status */
 292         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
 293                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 294                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 295
 296         clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
 297                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
 298                         EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 299
 300         /* Disable refreshed before leveling */
 301         clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
 302                         EMIF_REG_INITREF_DIS_MASK);
 303
 304         /* Start Full leveling */
 305         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 306
 307         __udelay(300);
 308
 309         /* Check for leveling timeout */
 310         if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
 311                 printf("Leveling timeout on EMIF%d\n", emif_num(base));
 312                 return;
 313         }
 314
 315         /* Enable refreshes after leveling */
 316         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 317
 318         debug("HW leveling success\n");
 319         /*
 320          * Update slave ratios in EXT_PHY_CTRLx registers
 321          * as per HW leveling output
 322          */
 323         update_hwleveling_output(base, regs);
 324 }
 325
 326 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
 327 {
 328         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 329
 330         if (warm_reset())
 331                 emif_reset_phy(base);
 332         do_ext_phy_settings(base, regs);
 333
 334         writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
 335                &emif->emif_sdram_ref_ctrl);
 336         /* Update timing registers */
 337         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 338         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 339         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 340
 341         writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
 342         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 343         writel(regs->zq_config, &emif->emif_zq_config);
 344         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 345         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 346         writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
 347
 348         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 349         writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
 350
 351         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 352
 353         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 354         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 355
 356         __udelay(1000);
 357
 358         writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
 359
 360         if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
 361                 dra7_ddr3_leveling(base, regs);
 362 }
 363
 364 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
 365 {
 366         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 367
 368         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 369         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 370         /*
 371          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 372          * and RL =7. As the default values of the Mode Registers are not
 373          * defined, contents of mode Registers must be fully initialized.
 374          * H/W takes care of this initialization
 375          */
 376         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 377
 378         /* Update timing registers */
 379         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 380         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 381         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 382
 383         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 384
 385         writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 386         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 387         do_ext_phy_settings(base, regs);
 388
 389         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 390         omap5_ddr3_leveling(base, regs);
 391 }
 392
 393 static void ddr3_init(u32 base, const struct emif_regs *regs)
 394 {
 395         if (is_omap54xx())
 396                 omap5_ddr3_init(base, regs);
 397         else
 398                 dra7_ddr3_init(base, regs);
 399 }
 400
 401 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 402 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 403
 404 /*
 405  * Organization and refresh requirements for LPDDR2 devices of different
 406  * types and densities. Derived from JESD209-2 section 2.4
 407  */
 408 const struct lpddr2_addressing addressing_table[] = {
 409         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 410         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 411         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 412         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 413         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 414         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 415         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 416         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 417         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 418         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 419         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 420 };
 421
 422 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 423         8,                      /* 64Mb */
 424         16,                     /* 128Mb */
 425         32,                     /* 256Mb */
 426         64,                     /* 512Mb */
 427         128,                    /* 1Gb   */
 428         256,                    /* 2Gb   */
 429         512,                    /* 4Gb   */
 430         1024,                   /* 8Gb   */
 431         2048,                   /* 16Gb  */
 432         4096                    /* 32Gb  */
 433 };
 434
 435 /*
 436  * Calculate the period of DDR clock from frequency value and set the
 437  * denominator and numerator in global variables for easy access later
 438  */
 439 static void set_ddr_clk_period(u32 freq)
 440 {
 441         /*
 442          * period = 1/freq
 443          * period_in_ns = 10^9/freq
 444          */
 445         *T_num = 1000000000;
 446         *T_den = freq;
 447         cancel_out(T_num, T_den, 200);
 448
 449 }
 450
 451 /*
 452  * Convert time in nano seconds to number of cycles of DDR clock
 453  */
 454 static inline u32 ns_2_cycles(u32 ns)
 455 {
 456         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 457 }
 458
 459 /*
 460  * ns_2_cycles with the difference that the time passed is 2 times the actual
 461  * value(to avoid fractions). The cycles returned is for the original value of
 462  * the timing parameter
 463  */
 464 static inline u32 ns_x2_2_cycles(u32 ns)
 465 {
 466         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 467 }
 468
 469 /*
 470  * Find addressing table index based on the device's type(S2 or S4) and
 471  * density
 472  */
 473 s8 addressing_table_index(u8 type, u8 density, u8 width)
 474 {
 475         u8 index;
 476         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 477                 return -1;
 478
 479         /*
 480          * Look at the way ADDR_TABLE_INDEX* values have been defined
 481          * in emif.h compared to LPDDR2_DENSITY_* values
 482          * The table is layed out in the increasing order of density
 483          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 484          * at the end
 485          */
 486         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 487                 index = ADDR_TABLE_INDEX1GS2;
 488         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 489                 index = ADDR_TABLE_INDEX2GS2;
 490         else
 491                 index = density;
 492
 493         debug("emif: addressing table index %d\n", index);
 494
 495         return index;
 496 }
 497
 498 /*
 499  * Find the the right timing table from the array of timing
 500  * tables of the device using DDR clock frequency
 501  */
 502 static const struct lpddr2_ac_timings *get_timings_table(const struct
 503                         lpddr2_ac_timings const *const *device_timings,
 504                         u32 freq)
 505 {
 506         u32 i, temp, freq_nearest;
 507         const struct lpddr2_ac_timings *timings = 0;
 508
 509         emif_assert(freq <= MAX_LPDDR2_FREQ);
 510         emif_assert(device_timings);
 511
 512         /*
 513          * Start with the maximum allowed frequency - that is always safe
 514          */
 515         freq_nearest = MAX_LPDDR2_FREQ;
 516         /*
 517          * Find the timings table that has the max frequency value:
 518          *   i.  Above or equal to the DDR frequency - safe
 519          *   ii. The lowest that satisfies condition (i) - optimal
 520          */
 521         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 522                 temp = device_timings[i]->max_freq;
 523                 if ((temp >= freq) && (temp <= freq_nearest)) {
 524                         freq_nearest = temp;
 525                         timings = device_timings[i];
 526                 }
 527         }
 528         debug("emif: timings table: %d\n", freq_nearest);
 529         return timings;
 530 }
 531
 532 /*
 533  * Finds the value of emif_sdram_config_reg
 534  * All parameters are programmed based on the device on CS0.
 535  * If there is a device on CS1, it will be same as that on CS0 or
 536  * it will be NVM. We don't support NVM yet.
 537  * If cs1_device pointer is NULL it is assumed that there is no device
 538  * on CS1
 539  */
 540 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 541                                 const struct lpddr2_device_details *cs1_device,
 542                                 const struct lpddr2_addressing *addressing,
 543                                 u8 RL)
 544 {
 545         u32 config_reg = 0;
 546
 547         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 548         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 549                         EMIF_REG_IBANK_POS_SHIFT;
 550
 551         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 552
 553         config_reg |= RL << EMIF_REG_CL_SHIFT;
 554
 555         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 556                         EMIF_REG_ROWSIZE_SHIFT;
 557
 558         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 559
 560         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 561                         EMIF_REG_EBANK_SHIFT;
 562
 563         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 564                         EMIF_REG_PAGESIZE_SHIFT;
 565
 566         return config_reg;
 567 }
 568
 569 static u32 get_sdram_ref_ctrl(u32 freq,
 570                               const struct lpddr2_addressing *addressing)
 571 {
 572         u32 ref_ctrl = 0, val = 0, freq_khz;
 573         freq_khz = freq / 1000;
 574         /*
 575          * refresh rate to be set is 'tREFI * freq in MHz
 576          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 577          */
 578         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 579         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 580
 581         return ref_ctrl;
 582 }
 583
 584 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 585                                const struct lpddr2_min_tck *min_tck,
 586                                const struct lpddr2_addressing *addressing)
 587 {
 588         u32 tim1 = 0, val = 0;
 589         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 590         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 591
 592         if (addressing->num_banks == BANKS8)
 593                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 594                                                         (4 * (*T_num)) - 1;
 595         else
 596                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 597
 598         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 599
 600         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 601         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 602
 603         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 604         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 605
 606         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 607         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 608
 609         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 610         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 611
 612         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 613         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 614
 615         return tim1;
 616 }
 617
 618 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 619                                const struct lpddr2_min_tck *min_tck)
 620 {
 621         u32 tim2 = 0, val = 0;
 622         val = max(min_tck->tCKE, timings->tCKE) - 1;
 623         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 624
 625         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 626         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 627
 628         /*
 629          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 630          * same value
 631          */
 632         val = ns_2_cycles(timings->tXSR) - 1;
 633         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 634         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 635
 636         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 637         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 638
 639         return tim2;
 640 }
 641
 642 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 643                                const struct lpddr2_min_tck *min_tck,
 644                                const struct lpddr2_addressing *addressing)
 645 {
 646         u32 tim3 = 0, val = 0;
 647         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 648         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 649
 650         val = ns_2_cycles(timings->tRFCab) - 1;
 651         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 652
 653         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 654         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 655
 656         val = ns_2_cycles(timings->tZQCS) - 1;
 657         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 658
 659         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 660         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 661
 662         return tim3;
 663 }
 664
 665 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 666                              const struct lpddr2_addressing *addressing,
 667                              u8 volt_ramp)
 668 {
 669         u32 zq = 0, val = 0;
 670         if (volt_ramp)
 671                 val =
 672                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 673                     addressing->t_REFI_us_x10;
 674         else
 675                 val =
 676                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 677                     addressing->t_REFI_us_x10;
 678         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 679
 680         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 681
 682         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 683
 684         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 685
 686         /*
 687          * Assuming that two chipselects have a single calibration resistor
 688          * If there are indeed two calibration resistors, then this flag should
 689          * be enabled to take advantage of dual calibration feature.
 690          * This data should ideally come from board files. But considering
 691          * that none of the boards today have calibration resistors per CS,
 692          * it would be an unnecessary overhead.
 693          */
 694         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 695
 696         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 697
 698         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 699
 700         return zq;
 701 }
 702
 703 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 704                                  const struct lpddr2_addressing *addressing,
 705                                  u8 is_derated)
 706 {
 707         u32 alert = 0, interval;
 708         interval =
 709             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 710         if (is_derated)
 711                 interval *= 4;
 712         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 713
 714         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 715
 716         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 717
 718         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 719
 720         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 721
 722         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 723
 724         return alert;
 725 }
 726
 727 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 728 {
 729         u32 idle = 0, val = 0;
 730         if (volt_ramp)
 731                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 732         else
 733                 /*Maximum value in normal conditions - suggested by hw team */
 734                 val = 0x1FF;
 735         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 736
 737         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 738
 739         return idle;
 740 }
 741
 742 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 743 {
 744         u32 phy = 0, val = 0;
 745
 746         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 747
 748         if (freq <= 100000000)
 749                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 750         else if (freq <= 200000000)
 751                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 752         else
 753                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 754         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 755
 756         /* Other fields are constant magic values. Hardcode them together */
 757         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 758                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 759
 760         return phy;
 761 }
 762
 763 static u32 get_emif_mem_size(u32 base)
 764 {
 765         u32 size_mbytes = 0, temp;
 766         struct emif_device_details dev_details;
 767         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 768         u32 emif_nr = emif_num(base);
 769
 770         emif_reset_phy(base);
 771         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 772                                                 &cs0_dev_details);
 773         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 774                                                 &cs1_dev_details);
 775         emif_reset_phy(base);
 776
 777         if (dev_details.cs0_device_details) {
 778                 temp = dev_details.cs0_device_details->density;
 779                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 780         }
 781
 782         if (dev_details.cs1_device_details) {
 783                 temp = dev_details.cs1_device_details->density;
 784                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 785         }
 786         /* convert to bytes */
 787         return size_mbytes << 20;
 788 }
 789
 790 /* Gets the encoding corresponding to a given DMM section size */
 791 u32 get_dmm_section_size_map(u32 section_size)
 792 {
 793         /*
 794          * Section size mapping:
 795          * 0x0: 16-MiB section
 796          * 0x1: 32-MiB section
 797          * 0x2: 64-MiB section
 798          * 0x3: 128-MiB section
 799          * 0x4: 256-MiB section
 800          * 0x5: 512-MiB section
 801          * 0x6: 1-GiB section
 802          * 0x7: 2-GiB section
 803          */
 804         section_size >>= 24; /* divide by 16 MB */
 805         return log_2_n_round_down(section_size);
 806 }
 807
 808 static void emif_calculate_regs(
 809                 const struct emif_device_details *emif_dev_details,
 810                 u32 freq, struct emif_regs *regs)
 811 {
 812         u32 temp, sys_freq;
 813         const struct lpddr2_addressing *addressing;
 814         const struct lpddr2_ac_timings *timings;
 815         const struct lpddr2_min_tck *min_tck;
 816         const struct lpddr2_device_details *cs0_dev_details =
 817                                         emif_dev_details->cs0_device_details;
 818         const struct lpddr2_device_details *cs1_dev_details =
 819                                         emif_dev_details->cs1_device_details;
 820         const struct lpddr2_device_timings *cs0_dev_timings =
 821                                         emif_dev_details->cs0_device_timings;
 822
 823         emif_assert(emif_dev_details);
 824         emif_assert(regs);
 825         /*
 826          * You can not have a device on CS1 without one on CS0
 827          * So configuring EMIF without a device on CS0 doesn't
 828          * make sense
 829          */
 830         emif_assert(cs0_dev_details);
 831         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 832         /*
 833          * If there is a device on CS1 it should be same type as CS0
 834          * (or NVM. But NVM is not supported in this driver yet)
 835          */
 836         emif_assert((cs1_dev_details == NULL) ||
 837                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 838                     (cs0_dev_details->type == cs1_dev_details->type));
 839         emif_assert(freq <= MAX_LPDDR2_FREQ);
 840
 841         set_ddr_clk_period(freq);
 842
 843         /*
 844          * The device on CS0 is used for all timing calculations
 845          * There is only one set of registers for timings per EMIF. So, if the
 846          * second CS(CS1) has a device, it should have the same timings as the
 847          * device on CS0
 848          */
 849         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 850         emif_assert(timings);
 851         min_tck = cs0_dev_timings->min_tck;
 852
 853         temp = addressing_table_index(cs0_dev_details->type,
 854                                       cs0_dev_details->density,
 855                                       cs0_dev_details->io_width);
 856
 857         emif_assert((temp >= 0));
 858         addressing = &(addressing_table[temp]);
 859         emif_assert(addressing);
 860
 861         sys_freq = get_sys_clk_freq();
 862
 863         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 864                                                         cs1_dev_details,
 865                                                         addressing, RL_BOOT);
 866
 867         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 868                                                 cs1_dev_details,
 869                                                 addressing, RL_FINAL);
 870
 871         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 872
 873         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 874
 875         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 876
 877         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 878
 879         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 880
 881         regs->temp_alert_config =
 882             get_temp_alert_config(cs1_dev_details, addressing, 0);
 883
 884         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 885                                             LPDDR2_VOLTAGE_STABLE);
 886
 887         regs->emif_ddr_phy_ctlr_1_init =
 888                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 889
 890         regs->emif_ddr_phy_ctlr_1 =
 891                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 892
 893         regs->freq = freq;
 894
 895         print_timing_reg(regs->sdram_config_init);
 896         print_timing_reg(regs->sdram_config);
 897         print_timing_reg(regs->ref_ctrl);
 898         print_timing_reg(regs->sdram_tim1);
 899         print_timing_reg(regs->sdram_tim2);
 900         print_timing_reg(regs->sdram_tim3);
 901         print_timing_reg(regs->read_idle_ctrl);
 902         print_timing_reg(regs->temp_alert_config);
 903         print_timing_reg(regs->zq_config);
 904         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 905         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 906 }
 907 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 908
 909 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 910 const char *get_lpddr2_type(u8 type_id)
 911 {
 912         switch (type_id) {
 913         case LPDDR2_TYPE_S4:
 914                 return "LPDDR2-S4";
 915         case LPDDR2_TYPE_S2:
 916                 return "LPDDR2-S2";
 917         default:
 918                 return NULL;
 919         }
 920 }
 921
 922 const char *get_lpddr2_io_width(u8 width_id)
 923 {
 924         switch (width_id) {
 925         case LPDDR2_IO_WIDTH_8:
 926                 return "x8";
 927         case LPDDR2_IO_WIDTH_16:
 928                 return "x16";
 929         case LPDDR2_IO_WIDTH_32:
 930                 return "x32";
 931         default:
 932                 return NULL;
 933         }
 934 }
 935
 936 const char *get_lpddr2_manufacturer(u32 manufacturer)
 937 {
 938         switch (manufacturer) {
 939         case LPDDR2_MANUFACTURER_SAMSUNG:
 940                 return "Samsung";
 941         case LPDDR2_MANUFACTURER_QIMONDA:
 942                 return "Qimonda";
 943         case LPDDR2_MANUFACTURER_ELPIDA:
 944                 return "Elpida";
 945         case LPDDR2_MANUFACTURER_ETRON:
 946                 return "Etron";
 947         case LPDDR2_MANUFACTURER_NANYA:
 948                 return "Nanya";
 949         case LPDDR2_MANUFACTURER_HYNIX:
 950                 return "Hynix";
 951         case LPDDR2_MANUFACTURER_MOSEL:
 952                 return "Mosel";
 953         case LPDDR2_MANUFACTURER_WINBOND:
 954                 return "Winbond";
 955         case LPDDR2_MANUFACTURER_ESMT:
 956                 return "ESMT";
 957         case LPDDR2_MANUFACTURER_SPANSION:
 958                 return "Spansion";
 959         case LPDDR2_MANUFACTURER_SST:
 960                 return "SST";
 961         case LPDDR2_MANUFACTURER_ZMOS:
 962                 return "ZMOS";
 963         case LPDDR2_MANUFACTURER_INTEL:
 964                 return "Intel";
 965         case LPDDR2_MANUFACTURER_NUMONYX:
 966                 return "Numonyx";
 967         case LPDDR2_MANUFACTURER_MICRON:
 968                 return "Micron";
 969         default:
 970                 return NULL;
 971         }
 972 }
 973
 974 static void display_sdram_details(u32 emif_nr, u32 cs,
 975                                   struct lpddr2_device_details *device)
 976 {
 977         const char *mfg_str;
 978         const char *type_str;
 979         char density_str[10];
 980         u32 density;
 981
 982         debug("EMIF%d CS%d\t", emif_nr, cs);
 983
 984         if (!device) {
 985                 debug("None\n");
 986                 return;
 987         }
 988
 989         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
 990         type_str = get_lpddr2_type(device->type);
 991
 992         density = lpddr2_density_2_size_in_mbytes[device->density];
 993         if ((density / 1024 * 1024) == density) {
 994                 density /= 1024;
 995                 sprintf(density_str, "%d GB", density);
 996         } else
 997                 sprintf(density_str, "%d MB", density);
 998         if (mfg_str && type_str)
 999                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
1000 }
1001
1002 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
1003                                   struct lpddr2_device_details *lpddr2_device)
1004 {
1005         u32 mr = 0, temp;
1006
1007         mr = get_mr(base, cs, LPDDR2_MR0);
1008         if (mr > 0xFF) {
1009                 /* Mode register value bigger than 8 bit */
1010                 return 0;
1011         }
1012
1013         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
1014         if (temp) {
1015                 /* Not SDRAM */
1016                 return 0;
1017         }
1018         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
1019
1020         if (temp) {
1021                 /* DNV supported - But DNV is only supported for NVM */
1022                 return 0;
1023         }
1024
1025         mr = get_mr(base, cs, LPDDR2_MR4);
1026         if (mr > 0xFF) {
1027                 /* Mode register value bigger than 8 bit */
1028                 return 0;
1029         }
1030
1031         mr = get_mr(base, cs, LPDDR2_MR5);
1032         if (mr > 0xFF) {
1033                 /* Mode register value bigger than 8 bit */
1034                 return 0;
1035         }
1036
1037         if (!get_lpddr2_manufacturer(mr)) {
1038                 /* Manufacturer not identified */
1039                 return 0;
1040         }
1041         lpddr2_device->manufacturer = mr;
1042
1043         mr = get_mr(base, cs, LPDDR2_MR6);
1044         if (mr >= 0xFF) {
1045                 /* Mode register value bigger than 8 bit */
1046                 return 0;
1047         }
1048
1049         mr = get_mr(base, cs, LPDDR2_MR7);
1050         if (mr >= 0xFF) {
1051                 /* Mode register value bigger than 8 bit */
1052                 return 0;
1053         }
1054
1055         mr = get_mr(base, cs, LPDDR2_MR8);
1056         if (mr >= 0xFF) {
1057                 /* Mode register value bigger than 8 bit */
1058                 return 0;
1059         }
1060
1061         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1062         if (!get_lpddr2_type(temp)) {
1063                 /* Not SDRAM */
1064                 return 0;
1065         }
1066         lpddr2_device->type = temp;
1067
1068         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1069         if (temp > LPDDR2_DENSITY_32Gb) {
1070                 /* Density not supported */
1071                 return 0;
1072         }
1073         lpddr2_device->density = temp;
1074
1075         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1076         if (!get_lpddr2_io_width(temp)) {
1077                 /* IO width unsupported value */
1078                 return 0;
1079         }
1080         lpddr2_device->io_width = temp;
1081
1082         /*
1083          * If all the above tests pass we should
1084          * have a device on this chip-select
1085          */
1086         return 1;
1087 }
1088
1089 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1090                         struct lpddr2_device_details *lpddr2_dev_details)
1091 {
1092         u32 phy;
1093         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1094
1095         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1096
1097         if (!lpddr2_dev_details)
1098                 return NULL;
1099
1100         /* Do the minimum init for mode register accesses */
1101         if (!(running_from_sdram() || warm_reset())) {
1102                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1103                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1104         }
1105
1106         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1107                 return NULL;
1108
1109         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1110
1111         return lpddr2_dev_details;
1112 }
1113 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1114
1115 static void do_sdram_init(u32 base)
1116 {
1117         const struct emif_regs *regs;
1118         u32 in_sdram, emif_nr;
1119
1120         debug(">>do_sdram_init() %x\n", base);
1121
1122         in_sdram = running_from_sdram();
1123         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1124
1125 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1126         emif_get_reg_dump(emif_nr, &regs);
1127         if (!regs) {
1128                 debug("EMIF: reg dump not provided\n");
1129                 return;
1130         }
1131 #else
1132         /*
1133          * The user has not provided the register values. We need to
1134          * calculate it based on the timings and the DDR frequency
1135          */
1136         struct emif_device_details dev_details;
1137         struct emif_regs calculated_regs;
1138
1139         /*
1140          * Get device details:
1141          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1142          * - Obtained from user otherwise
1143          */
1144         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1145         emif_reset_phy(base);
1146         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1147                                                 &cs0_dev_details);
1148         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1149                                                 &cs1_dev_details);
1150         emif_reset_phy(base);
1151
1152         /* Return if no devices on this EMIF */
1153         if (!dev_details.cs0_device_details &&
1154             !dev_details.cs1_device_details) {
1155                 return;
1156         }
1157
1158         /*
1159          * Get device timings:
1160          * - Default timings specified by JESD209-2 if
1161          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1162          * - Obtained from user otherwise
1163          */
1164         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1165                                 &dev_details.cs1_device_timings);
1166
1167         /* Calculate the register values */
1168         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1169         regs = &calculated_regs;
1170 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1171
1172         /*
1173          * Initializing the LPDDR2 device can not happen from SDRAM.
1174          * Changing the timing registers in EMIF can happen(going from one
1175          * OPP to another)
1176          */
1177         if (!in_sdram && (!warm_reset() || is_dra7xx())) {
1178                 if (emif_sdram_type(regs->sdram_config) ==
1179                     EMIF_SDRAM_TYPE_LPDDR2)
1180                         lpddr2_init(base, regs);
1181                 else
1182                         ddr3_init(base, regs);
1183         }
1184         if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
1185             EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
1186                 set_lpmode_selfrefresh(base);
1187                 emif_reset_phy(base);
1188                 omap5_ddr3_leveling(base, regs);
1189         }
1190
1191         /* Write to the shadow registers */
1192         emif_update_timings(base, regs);
1193
1194         debug("<<do_sdram_init() %x\n", base);
1195 }
1196
1197 void emif_post_init_config(u32 base)
1198 {
1199         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1200         u32 omap_rev = omap_revision();
1201
1202         /* reset phy on ES2.0 */
1203         if (omap_rev == OMAP4430_ES2_0)
1204                 emif_reset_phy(base);
1205
1206         /* Put EMIF back in smart idle on ES1.0 */
1207         if (omap_rev == OMAP4430_ES1_0)
1208                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1209 }
1210
1211 void dmm_init(u32 base)
1212 {
1213         const struct dmm_lisa_map_regs *lisa_map_regs;
1214         u32 i, section, valid;
1215
1216 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1217         emif_get_dmm_regs(&lisa_map_regs);
1218 #else
1219         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1220         u32 section_cnt, sys_addr;
1221         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1222
1223         mapped_size = 0;
1224         section_cnt = 3;
1225         sys_addr = CONFIG_SYS_SDRAM_BASE;
1226         emif1_size = get_emif_mem_size(EMIF1_BASE);
1227         emif2_size = get_emif_mem_size(EMIF2_BASE);
1228         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1229
1230         if (!emif1_size && !emif2_size)
1231                 return;
1232
1233         /* symmetric interleaved section */
1234         if (emif1_size && emif2_size) {
1235                 mapped_size = min(emif1_size, emif2_size);
1236                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1237                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1238                 /* only MSB */
1239                 section_map |= (sys_addr >> 24) <<
1240                                 EMIF_SYS_ADDR_SHIFT;
1241                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1242                                 << EMIF_SYS_SIZE_SHIFT;
1243                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1244                 emif1_size -= mapped_size;
1245                 emif2_size -= mapped_size;
1246                 sys_addr += (mapped_size * 2);
1247                 section_cnt--;
1248         }
1249
1250         /*
1251          * Single EMIF section(we can have a maximum of 1 single EMIF
1252          * section- either EMIF1 or EMIF2 or none, but not both)
1253          */
1254         if (emif1_size) {
1255                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1256                 section_map |= get_dmm_section_size_map(emif1_size)
1257                                 << EMIF_SYS_SIZE_SHIFT;
1258                 /* only MSB */
1259                 section_map |= (mapped_size >> 24) <<
1260                                 EMIF_SDRC_ADDR_SHIFT;
1261                 /* only MSB */
1262                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1263                 section_cnt--;
1264         }
1265         if (emif2_size) {
1266                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1267                 section_map |= get_dmm_section_size_map(emif2_size) <<
1268                                 EMIF_SYS_SIZE_SHIFT;
1269                 /* only MSB */
1270                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1271                 /* only MSB */
1272                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1273                 section_cnt--;
1274         }
1275
1276         if (section_cnt == 2) {
1277                 /* Only 1 section - either symmetric or single EMIF */
1278                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1279                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1280                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1281         } else {
1282                 /* 2 sections - 1 symmetric, 1 single EMIF */
1283                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1284                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1285         }
1286
1287         /* TRAP for invalid TILER mappings in section 0 */
1288         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1289
1290         if (omap_revision() >= OMAP4460_ES1_0)
1291                 lis_map_regs_calculated.is_ma_present = 1;
1292
1293         lisa_map_regs = &lis_map_regs_calculated;
1294 #endif
1295         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1296             (struct dmm_lisa_map_regs *)base;
1297
1298         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1299         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1300         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1301         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1302
1303         writel(lisa_map_regs->dmm_lisa_map_3,
1304                 &hw_lisa_map_regs->dmm_lisa_map_3);
1305         writel(lisa_map_regs->dmm_lisa_map_2,
1306                 &hw_lisa_map_regs->dmm_lisa_map_2);
1307         writel(lisa_map_regs->dmm_lisa_map_1,
1308                 &hw_lisa_map_regs->dmm_lisa_map_1);
1309         writel(lisa_map_regs->dmm_lisa_map_0,
1310                 &hw_lisa_map_regs->dmm_lisa_map_0);
1311
1312         if (lisa_map_regs->is_ma_present) {
1313                 hw_lisa_map_regs =
1314                     (struct dmm_lisa_map_regs *)MA_BASE;
1315
1316                 writel(lisa_map_regs->dmm_lisa_map_3,
1317                         &hw_lisa_map_regs->dmm_lisa_map_3);
1318                 writel(lisa_map_regs->dmm_lisa_map_2,
1319                         &hw_lisa_map_regs->dmm_lisa_map_2);
1320                 writel(lisa_map_regs->dmm_lisa_map_1,
1321                         &hw_lisa_map_regs->dmm_lisa_map_1);
1322                 writel(lisa_map_regs->dmm_lisa_map_0,
1323                         &hw_lisa_map_regs->dmm_lisa_map_0);
1324         }
1325
1326         /*
1327          * EMIF should be configured only when
1328          * memory is mapped on it. Using emif1_enabled
1329          * and emif2_enabled variables for this.
1330          */
1331         emif1_enabled = 0;
1332         emif2_enabled = 0;
1333         for (i = 0; i < 4; i++) {
1334                 section = __raw_readl(DMM_BASE + i*4);
1335                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1336                         (EMIF_SDRC_MAP_SHIFT);
1337                 if (valid == 3) {
1338                         emif1_enabled = 1;
1339                         emif2_enabled = 1;
1340                         break;
1341                 }
1342
1343                 if (valid == 1)
1344                         emif1_enabled = 1;
1345
1346                 if (valid == 2)
1347                         emif2_enabled = 1;
1348         }
1349 }
1350
1351 static void do_bug0039_workaround(u32 base)
1352 {
1353         u32 val, i, clkctrl;
1354         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1355         const struct read_write_regs *bug_00339_regs;
1356         u32 iterations;
1357         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1358         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1359
1360         if (is_dra7xx())
1361                 phy_status_base++;
1362
1363         bug_00339_regs = get_bug_regs(&iterations);
1364
1365         /* Put EMIF in to idle */
1366         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1367         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1368
1369         /* Copy the phy status registers in to phy ctrl shadow registers */
1370         for (i = 0; i < iterations; i++) {
1371                 val = __raw_readl(phy_status_base +
1372                                   bug_00339_regs[i].read_reg - 1);
1373
1374                 __raw_writel(val, phy_ctrl_base +
1375                              ((bug_00339_regs[i].write_reg - 1) << 1));
1376
1377                 __raw_writel(val, phy_ctrl_base +
1378                              (bug_00339_regs[i].write_reg << 1) - 1);
1379         }
1380
1381         /* Disable leveling */
1382         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1383
1384         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1385 }
1386
1387 /*
1388  * SDRAM initialization:
1389  * SDRAM initialization has two parts:
1390  * 1. Configuring the SDRAM device
1391  * 2. Update the AC timings related parameters in the EMIF module
1392  * (1) should be done only once and should not be done while we are
1393  * running from SDRAM.
1394  * (2) can and should be done more than once if OPP changes.
1395  * Particularly, this may be needed when we boot without SPL and
1396  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1397  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1398  * the frequency. So,
1399  * Doing (1) and (2) makes sense - first time initialization
1400  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1401  * Doing (1) and not (2) doen't make sense
1402  * See do_sdram_init() for the details
1403  */
1404 void sdram_init(void)
1405 {
1406         u32 in_sdram, size_prog, size_detect;
1407         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1408         u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
1409
1410         debug(">>sdram_init()\n");
1411
1412         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1413                 return;
1414
1415         in_sdram = running_from_sdram();
1416         debug("in_sdram = %d\n", in_sdram);
1417
1418         if (!in_sdram) {
1419                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1420                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1421                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1422                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1423         }
1424
1425         if (!in_sdram)
1426                 dmm_init(DMM_BASE);
1427
1428         if (emif1_enabled)
1429                 do_sdram_init(EMIF1_BASE);
1430
1431         if (emif2_enabled)
1432                 do_sdram_init(EMIF2_BASE);
1433
1434         if (!(in_sdram || warm_reset())) {
1435                 if (emif1_enabled)
1436                         emif_post_init_config(EMIF1_BASE);
1437                 if (emif2_enabled)
1438                         emif_post_init_config(EMIF2_BASE);
1439         }
1440
1441         /* for the shadow registers to take effect */
1442         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1443                 freq_update_core();
1444
1445         /* Do some testing after the init */
1446         if (!in_sdram) {
1447                 size_prog = omap_sdram_size();
1448                 size_prog = log_2_n_round_down(size_prog);
1449                 size_prog = (1 << size_prog);
1450
1451                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1452                                                 size_prog);
1453                 /* Compare with the size programmed */
1454                 if (size_detect != size_prog) {
1455                         printf("SDRAM: identified size not same as expected"
1456                                 " size identified: %x expected: %x\n",
1457                                 size_detect,
1458                                 size_prog);
1459                 } else
1460                         debug("get_ram_size() successful");
1461         }
1462
1463         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1464             (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1465                 if (emif1_enabled)
1466                         do_bug0039_workaround(EMIF1_BASE);
1467                 if (emif2_enabled)
1468                         do_bug0039_workaround(EMIF2_BASE);
1469         }
1470
1471         debug("<<sdram_init()\n");
1472 }