3 * Common functions for OMAP4/5 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/sys_proto.h>
33 #include <asm/sizes.h>
35 #include <asm/omap_common.h>
36 #include <linux/compiler.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
43 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
45 for (i = 0; i < size; i++, pad++)
46 writew(pad->val, base + pad->offset);
49 static void set_mux_conf_regs(void)
51 switch (omap_hw_init_context()) {
52 case OMAP_INIT_CONTEXT_SPL:
53 set_muxconf_regs_essential();
55 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
56 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
57 set_muxconf_regs_non_essential();
60 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
61 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
62 set_muxconf_regs_essential();
63 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
64 set_muxconf_regs_non_essential();
75 /* Read Main ID Register (MIDR) */
76 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
81 void omap_rev_string(void)
83 u32 omap_rev = omap_revision();
84 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
85 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
86 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
87 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
93 printf("%x ES%x.%x\n", omap_variant, major_rev,
97 #ifdef CONFIG_SPL_BUILD
98 static void init_boot_params(void)
100 boot_params_ptr = (u32 *) &boot_params;
103 void spl_display_print(void)
109 void __weak srcomp_enable(void)
115 * Description: Does early system init of watchdog, muxing, andclocks
116 * Watchdog disable is done always. For the rest what gets done
117 * depends on the boot mode in which this function is executed
118 * 1. s_init of SPL running from SRAM
119 * 2. s_init of U-Boot running from FLASH
120 * 3. s_init of U-Boot loaded to SDRAM by SPL
121 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
122 * Configuration Header feature
123 * Please have a look at the respective functions to see what gets
124 * done in each of these cases
125 * This function is called with SRAM stack.
129 init_omap_revision();
132 #ifdef CONFIG_SPL_BUILD
133 if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
134 force_emif_self_refresh();
138 #ifdef CONFIG_SPL_BUILD
140 setup_clocks_for_console();
144 preloader_console_init();
148 #ifdef CONFIG_SPL_BUILD
151 /* For regular u-boot sdram_init() is called from dram_init() */
158 * Routine: wait_for_command_complete
159 * Description: Wait for posting to finish on watchdog
161 void wait_for_command_complete(struct watchdog *wd_base)
165 pending = readl(&wd_base->wwps);
170 * Routine: watchdog_init
171 * Description: Shut down watch dogs
173 void watchdog_init(void)
175 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
177 writel(WD_UNLOCK1, &wd2_base->wspr);
178 wait_for_command_complete(wd2_base);
179 writel(WD_UNLOCK2, &wd2_base->wspr);
184 * This function finds the SDRAM size available in the system
185 * based on DMM section configurations
186 * This is needed because the size of memory installed may be
187 * different on different versions of the board
189 u32 omap_sdram_size(void)
191 u32 section, i, valid;
192 u64 sdram_start = 0, sdram_end = 0, addr,
193 size, total_size = 0, trap_size = 0;
195 for (i = 0; i < 4; i++) {
196 section = __raw_readl(DMM_BASE + i*4);
197 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
198 (EMIF_SDRC_ADDRSPC_SHIFT);
199 addr = section & EMIF_SYS_ADDR_MASK;
201 /* See if the address is valid */
202 if ((addr >= DRAM_ADDR_SPACE_START) &&
203 (addr < DRAM_ADDR_SPACE_END)) {
204 size = ((section & EMIF_SYS_SIZE_MASK) >>
205 EMIF_SYS_SIZE_SHIFT);
209 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
210 if (!sdram_start || (addr < sdram_start))
212 if (!sdram_end || ((addr + size) > sdram_end))
213 sdram_end = addr + size;
221 total_size = (sdram_end - sdram_start) - (trap_size);
229 * Description: sets uboots idea of sdram size
234 gd->ram_size = omap_sdram_size();
239 * Print board information
243 puts(sysinfo.board_string);
248 * get_device_type(): tell if GP/HS/EMU/TST
250 u32 get_device_type(void)
252 return (readl((*ctrl)->control_status) &
253 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
257 * Print CPU information
259 int print_cpuinfo(void)
266 #ifndef CONFIG_SYS_DCACHE_OFF
267 void enable_caches(void)
269 /* Enable D-cache. I-cache is already enabled in start.S */