3 * Common functions for OMAP4/5 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/sys_proto.h>
17 #include <asm/sizes.h>
19 #include <asm/omap_common.h>
20 #include <linux/compiler.h>
21 #include <asm/cache.h>
22 #include <asm/system.h>
24 #define ARMV7_DCACHE_WRITEBACK 0xe
25 #define ARMV7_DOMAIN_CLIENT 1
26 #define ARMV7_DOMAIN_MASK (0x3 << 0)
28 DECLARE_GLOBAL_DATA_PTR;
30 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
33 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
35 for (i = 0; i < size; i++, pad++)
36 writew(pad->val, base + pad->offset);
39 static void set_mux_conf_regs(void)
41 switch (omap_hw_init_context()) {
42 case OMAP_INIT_CONTEXT_SPL:
43 set_muxconf_regs_essential();
45 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
46 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
47 set_muxconf_regs_non_essential();
50 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
51 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
52 set_muxconf_regs_essential();
53 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
54 set_muxconf_regs_non_essential();
65 /* Read Main ID Register (MIDR) */
66 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
71 static void omap_rev_string(void)
73 u32 omap_rev = omap_revision();
74 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
75 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
76 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
77 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
83 printf("%x ES%x.%x\n", omap_variant, major_rev,
87 #ifdef CONFIG_SPL_BUILD
88 void spl_display_print(void)
94 void __weak srcomp_enable(void)
98 #ifdef CONFIG_ARCH_CPU_INIT
100 * SOC specific cpu init
102 int arch_cpu_init(void)
104 save_omap_boot_params();
107 #endif /* CONFIG_ARCH_CPU_INIT */
111 * Description: Does early system init of watchdog, muxing, andclocks
112 * Watchdog disable is done always. For the rest what gets done
113 * depends on the boot mode in which this function is executed
114 * 1. s_init of SPL running from SRAM
115 * 2. s_init of U-Boot running from FLASH
116 * 3. s_init of U-Boot loaded to SDRAM by SPL
117 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
118 * Configuration Header feature
119 * Please have a look at the respective functions to see what gets
120 * done in each of these cases
121 * This function is called with SRAM stack.
126 * Save the boot parameters passed from romcode.
127 * We cannot delay the saving further than this,
128 * to prevent overwrites.
130 #ifdef CONFIG_SPL_BUILD
131 save_omap_boot_params();
133 init_omap_revision();
136 #ifdef CONFIG_SPL_BUILD
137 if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
138 force_emif_self_refresh();
142 #ifdef CONFIG_SPL_BUILD
144 setup_clocks_for_console();
148 preloader_console_init();
152 #ifdef CONFIG_SPL_BUILD
153 /* For regular u-boot sdram_init() is called from dram_init() */
159 * Routine: wait_for_command_complete
160 * Description: Wait for posting to finish on watchdog
162 void wait_for_command_complete(struct watchdog *wd_base)
166 pending = readl(&wd_base->wwps);
171 * Routine: watchdog_init
172 * Description: Shut down watch dogs
174 void watchdog_init(void)
176 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
178 writel(WD_UNLOCK1, &wd2_base->wspr);
179 wait_for_command_complete(wd2_base);
180 writel(WD_UNLOCK2, &wd2_base->wspr);
185 * This function finds the SDRAM size available in the system
186 * based on DMM section configurations
187 * This is needed because the size of memory installed may be
188 * different on different versions of the board
190 u32 omap_sdram_size(void)
192 u32 section, i, valid;
193 u64 sdram_start = 0, sdram_end = 0, addr,
194 size, total_size = 0, trap_size = 0;
196 for (i = 0; i < 4; i++) {
197 section = __raw_readl(DMM_BASE + i*4);
198 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
199 (EMIF_SDRC_ADDRSPC_SHIFT);
200 addr = section & EMIF_SYS_ADDR_MASK;
202 /* See if the address is valid */
203 if ((addr >= DRAM_ADDR_SPACE_START) &&
204 (addr < DRAM_ADDR_SPACE_END)) {
205 size = ((section & EMIF_SYS_SIZE_MASK) >>
206 EMIF_SYS_SIZE_SHIFT);
210 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
211 if (!sdram_start || (addr < sdram_start))
213 if (!sdram_end || ((addr + size) > sdram_end))
214 sdram_end = addr + size;
222 total_size = (sdram_end - sdram_start) - (trap_size);
230 * Description: sets uboots idea of sdram size
235 gd->ram_size = omap_sdram_size();
240 * Print board information
244 puts(sysinfo.board_string);
249 * get_device_type(): tell if GP/HS/EMU/TST
251 u32 get_device_type(void)
253 return (readl((*ctrl)->control_status) &
254 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
258 * Print CPU information
260 int print_cpuinfo(void)
267 #ifndef CONFIG_SYS_DCACHE_OFF
268 void enable_caches(void)
270 /* Enable D-cache. I-cache is already enabled in start.S */
274 void dram_bank_mmu_setup(int bank)
279 u32 start = bd->bi_dram[bank].start >> 20;
280 u32 size = bd->bi_dram[bank].size >> 20;
281 u32 end = start + size;
283 debug("%s: bank: %d\n", __func__, bank);
284 for (i = start; i < end; i++)
285 set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
289 void arm_init_domains(void)
295 * Set DOMAIN to client access so that all permissions
296 * set in pagetables are validated by the mmu.
298 reg &= ~ARMV7_DOMAIN_MASK;
299 reg |= ARMV7_DOMAIN_CLIENT;