2 * This file configures the internal USB PHY in AM35X.
4 * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
6 * Based on omap_phy_internal.c code from Linux by
7 * Hema HK <hemahk@ti.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
27 #include <asm/arch/am35x_def.h>
29 void am35x_musb_reset(void)
31 /* Reset the musb interface */
32 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
34 clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
38 void am35x_musb_phy_power(u8 on)
40 unsigned long start = get_timer(0);
44 * Start the on-chip PHY and its PLL.
46 clrsetbits_le32(&am35x_scm_general_regs->devconf2,
47 CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
50 debug("Waiting for PHY clock good...\n");
51 while (!(readl(&am35x_scm_general_regs->devconf2)
54 if (get_timer(start) > CONFIG_SYS_HZ / 10) {
55 printf("musb PHY clock good timed out\n");
61 * Power down the on-chip PHY.
63 clrsetbits_le32(&am35x_scm_general_regs->devconf2,
65 CONF2_PHYPWRDN | CONF2_OTGPWRDN);
69 void am35x_musb_clear_irq(void)
71 clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
73 readl(&am35x_scm_general_regs->lvl_intr_clr);