3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/mem.h>
39 #include <asm/cache.h>
40 #include <asm/armv7.h>
41 #include <asm/arch/gpio.h>
43 #include <asm/omap_common.h>
45 #include <linux/compiler.h>
48 extern omap3_sysinfo sysinfo;
49 static void omap3_setup_aux_cr(void);
50 static void omap3_invalidate_l2_cache_secure(void);
52 static const struct gpio_bank gpio_bank_34xx[6] = {
53 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
54 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
55 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
56 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
57 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
58 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
61 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
63 #ifdef CONFIG_SPL_BUILD
65 * We use static variables because global data is not ready yet.
66 * Initialized data is available in SPL right from the beginning.
67 * We would not typically need to save these parameters in regular
68 * U-Boot. This is needed only in SPL at the moment.
70 u32 omap3_boot_device = BOOT_DEVICE_NAND;
72 /* auto boot mode detection is not possible for OMAP3 - hard code */
73 u32 spl_boot_mode(void)
75 switch (spl_boot_device()) {
76 case BOOT_DEVICE_MMC2:
77 return MMCSD_MODE_RAW;
78 case BOOT_DEVICE_MMC1:
79 return MMCSD_MODE_FAT;
82 puts("spl: ERROR: unknown device - can't select boot mode\n");
87 u32 spl_boot_device(void)
89 return omap3_boot_device;
92 void spl_board_init(void)
94 #ifdef CONFIG_SPL_I2C_SUPPORT
95 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
98 #endif /* CONFIG_SPL_BUILD */
101 /******************************************************************************
102 * Routine: secure_unlock
103 * Description: Setup security registers for access
105 *****************************************************************************/
106 void secure_unlock_mem(void)
108 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
109 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
110 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
111 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
112 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
114 /* Protection Module Register Target APE (PM_RT) */
115 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
116 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
117 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
118 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
120 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
121 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
122 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
124 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
125 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
126 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
127 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
130 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
131 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
132 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
134 /* SDRC region 0 public */
135 writel(UNLOCK_1, &sms_base->rg_att0);
138 /******************************************************************************
139 * Routine: secureworld_exit()
140 * Description: If chip is EMU and boot type is external
141 * configure secure registers and exit secure world
143 *****************************************************************************/
144 void secureworld_exit()
148 /* configure non-secure access control register */
149 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
150 /* enabling co-processor CP10 and CP11 accesses in NS world */
151 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
153 * allow allocation of locked TLBs and L2 lines in NS world
154 * allow use of PLE registers in NS world also
156 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
157 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
159 /* Enable ASA in ACR register */
160 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
161 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
162 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
164 /* Exiting secure world */
165 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
166 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
167 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
170 /******************************************************************************
171 * Routine: try_unlock_sram()
172 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
174 *****************************************************************************/
175 void try_unlock_memory()
178 int in_sdram = is_running_in_sdram();
181 * if GP device unlock device SRAM for general use
182 * secure code breaks for Secure/Emulation device - HS/E/T
184 mode = get_device_type();
185 if (mode == GP_DEVICE)
189 * If device is EMU and boot is XIP external booting
190 * Unlock firewalls and disable L2 and put chip
191 * out of secure world
193 * Assuming memories are unlocked by the demon who put us in SDRAM
195 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
204 /******************************************************************************
206 * Description: Does early system init of muxing and clocks.
207 * - Called path is with SRAM stack.
208 *****************************************************************************/
211 int in_sdram = is_running_in_sdram();
217 /* Errata workarounds */
218 omap3_setup_aux_cr();
220 #ifndef CONFIG_SYS_L2CACHE_OFF
221 /* Invalidate L2-cache from secure mode */
222 omap3_invalidate_l2_cache_secure();
232 #ifdef CONFIG_USB_EHCI_OMAP
233 ehci_clocks_enable();
236 #ifdef CONFIG_SPL_BUILD
237 preloader_console_init();
247 * Routine: misc_init_r
248 * Description: A basic misc_init_r that just displays the die ID
250 int __weak misc_init_r(void)
257 /******************************************************************************
258 * Routine: wait_for_command_complete
259 * Description: Wait for posting to finish on watchdog
260 *****************************************************************************/
261 void wait_for_command_complete(struct watchdog *wd_base)
265 pending = readl(&wd_base->wwps);
269 /******************************************************************************
270 * Routine: watchdog_init
271 * Description: Shut down watch dogs
272 *****************************************************************************/
273 void watchdog_init(void)
275 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
276 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
279 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
280 * either taken care of by ROM (HS/EMU) or not accessible (GP).
281 * We need to take care of WD2-MPU or take a PRCM reset. WD3
282 * should not be running and does not generate a PRCM reset.
285 sr32(&prcm_base->fclken_wkup, 5, 1, 1);
286 sr32(&prcm_base->iclken_wkup, 5, 1, 1);
287 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
289 writel(WD_UNLOCK1, &wd2_base->wspr);
290 wait_for_command_complete(wd2_base);
291 writel(WD_UNLOCK2, &wd2_base->wspr);
294 /******************************************************************************
295 * Dummy function to handle errors for EABI incompatibility
296 *****************************************************************************/
301 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
302 /******************************************************************************
303 * OMAP3 specific command to switch between NAND HW and SW ecc
304 *****************************************************************************/
305 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
309 if (strncmp(argv[1], "hw", 2) == 0)
310 omap_nand_switch_ecc(1);
311 else if (strncmp(argv[1], "sw", 2) == 0)
312 omap_nand_switch_ecc(0);
319 printf ("Usage: nandecc %s\n", cmdtp->usage);
324 nandecc, 2, 1, do_switch_ecc,
325 "switch OMAP3 NAND ECC calculation algorithm",
326 "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
329 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
331 #ifdef CONFIG_DISPLAY_BOARDINFO
333 * Print board information
335 int checkboard (void)
344 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
345 sysinfo.nand_string);
349 #endif /* CONFIG_DISPLAY_BOARDINFO */
351 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
353 u32 i, num_params = *parameters;
354 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
357 * copy the parameters to an un-cached area to avoid coherency
360 for (i = 0; i < num_params; i++) {
361 __raw_writel(*parameters, sram_scratch_space);
363 sram_scratch_space++;
366 /* Now make the PPA call */
367 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
370 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
375 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
379 if (get_device_type() == GP_DEVICE) {
380 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
383 struct emu_hal_params emu_romcode_params;
384 emu_romcode_params.num_params = 1;
385 emu_romcode_params.param1 = acr;
386 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
387 (u32 *)&emu_romcode_params);
391 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
396 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
400 /* Write ACR - affects non-secure banked bits */
401 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
404 static void omap3_setup_aux_cr(void)
406 /* Workaround for Cortex-A8 errata: #454179 #430973
408 * Set "Disable Branch Size Mispredicts" bit
409 * Workaround for erratum #621766
411 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
413 omap3_update_aux_cr_secure(0xE0, 0);
416 #ifndef CONFIG_SYS_L2CACHE_OFF
417 /* Invalidate the entire L2 cache from secure mode */
418 static void omap3_invalidate_l2_cache_secure(void)
420 if (get_device_type() == GP_DEVICE) {
421 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
424 struct emu_hal_params emu_romcode_params;
425 emu_romcode_params.num_params = 1;
426 emu_romcode_params.param1 = 0;
427 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
428 (u32 *)&emu_romcode_params);
432 void v7_outer_cache_enable(void)
435 omap3_update_aux_cr_secure(0x2, 0);
438 * On some revisions L2EN bit is banked on some revisions it's not
439 * No harm in setting both banked bits(in fact this is required
442 omap3_update_aux_cr(0x2, 0);
445 void omap3_outer_cache_disable(void)
448 omap3_update_aux_cr_secure(0, 0x2);
451 * On some revisions L2EN bit is banked on some revisions it's not
452 * No harm in clearing both banked bits(in fact this is required
455 omap3_update_aux_cr(0, 0x2);
459 #ifndef CONFIG_SYS_DCACHE_OFF
460 void enable_caches(void)
462 /* Enable D-cache. I-cache is already enabled in start.S */