2 * Copyright (c) 2009 Wind River Systems, Inc.
3 * Tom Rix <Tom.Rix@windriver.com>
5 * This file is based on and replaces the existing cache.c file
6 * The copyrights for the cache.c file are:
8 * (C) Copyright 2008 Texas Insturments
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Marius Groeger <mgroeger@sysgo.de>
15 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/omap3.h>
43 .global invalidate_dcache
44 .global l2_cache_enable
45 .global l2_cache_disable
51 * Invalidate the whole D-cache.
53 * Corrupted registers: r0-r5, r7, r9-r11
55 * - mm - mm_struct describing address space
58 stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
60 mov r7, r0 @ take a backup of device type
61 cmp r0, #0x3 @ check if the device type is
63 moveq r12, #0x1 @ set up to invalide L2
64 smi: .word 0x01600070 @ Call SMI monitor (smieq)
65 cmp r7, #0x3 @ compare again in case its
67 beq finished_inval @ if GP device, inval done
70 mrc p15, 1, r0, c0, c0, 1 @ read clidr
71 ands r3, r0, #0x7000000 @ extract loc from clidr
72 mov r3, r3, lsr #23 @ left align loc bit field
73 beq finished_inval @ if loc is 0, then no need to
75 mov r10, #0 @ start clean at cache level 0
77 add r2, r10, r10, lsr #1 @ work out 3x current cache
79 mov r1, r0, lsr r2 @ extract cache type bits from
81 and r1, r1, #7 @ mask of the bits for current
83 cmp r1, #2 @ see what cache we have at
85 blt skip_inval @ skip if no cache, or just
87 mcr p15, 2, r10, c0, c0, 0 @ select current cache level
89 mov r2, #0 @ operand for mcr SBZ
90 mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
91 @ sych the new cssr&csidr,
92 @ with armv7 this is 'isb',
93 @ but we compile with armv5
94 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
95 and r2, r1, #7 @ extract the length of the
97 add r2, r2, #4 @ add 4 (line length offset)
99 ands r4, r4, r1, lsr #3 @ find maximum number on the
101 clz r5, r4 @ find bit position of way
104 ands r7, r7, r1, lsr #13 @ extract max number of the
107 mov r9, r4 @ create working copy of max
110 orr r11, r10, r9, lsl r5 @ factor way and cache number
112 orr r11, r11, r7, lsl r2 @ factor index number into r11
113 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
114 subs r9, r9, #1 @ decrement the way
116 subs r7, r7, #1 @ decrement the index
119 add r10, r10, #2 @ increment cache number
123 mov r10, #0 @ swith back to cache level 0
124 mcr p15, 2, r10, c0, c0, 0 @ select current cache level
126 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
127 @ with armv7 this is 'isb',
128 @ but we compile with armv5
130 ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
133 stmfd r13!, {r4 - r6, lr}
138 @ ES2 onwards we can disable/enable L2 ourselves
139 cmp r0, #CPU_OMAP34XX
140 cmpeq r4, #CPU_3XX_ES10
141 mrc 15, 0, r0, cr1, cr0, 1
143 orr r0, r0, r5, lsl #1
144 mcreq 15, 0, r0, cr1, cr0, 1
145 @ GP Device ROM code API usage here
146 @ r12 = AUXCR Write function and r0 value
148 @ SMCNE instruction to call ROM Code API
150 ldmfd r13!, {r4 - r6, pc}
160 /******************************************************************************
161 * Routine: setup_auxcr()
162 * Description: Write to AuxCR desired value using SMI.
164 *****************************************************************************/
166 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
167 and r2, r0, #0x00f00000 @ variant
168 and r3, r0, #0x0000000f @ revision
169 orr r1, r3, r2, lsr #20-4 @ combine variant and revision
171 mrc p15, 0, r0, c1, c0, 1
172 orr r0, r0, #0x10 @ Enable ASA
173 @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
175 orrlt r0, r0, #1 << 5
176 .word 0xE1600070 @ SMC
178 mrc p15, 1, r0, c9, c0, 2
179 @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
181 orrlt r0, r0, #1 << 27
182 .word 0xE1600070 @ SMC
186 .global v7_flush_dcache_all
187 .global v7_flush_cache_all
190 * v7_flush_dcache_all()
192 * Flush the whole D-cache.
194 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
196 * - mm - mm_struct describing address space
199 # dmb @ ensure ordering with previous memory accesses
200 mrc p15, 1, r0, c0, c0, 1 @ read clidr
201 ands r3, r0, #0x7000000 @ extract loc from clidr
202 mov r3, r3, lsr #23 @ left align loc bit field
203 beq finished @ if loc is 0, then no need to clean
204 mov r10, #0 @ start clean at cache level 0
206 add r2, r10, r10, lsr #1 @ work out 3x current cache level
207 mov r1, r0, lsr r2 @ extract cache type bits from clidr
208 and r1, r1, #7 @ mask of the bits for current cache only
209 cmp r1, #2 @ see what cache we have at this level
210 blt skip @ skip if no cache, or just i-cache
211 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
212 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
213 @ with armv7 this is 'isb',
214 @ but we compile with armv5
215 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
216 and r2, r1, #7 @ extract the length of the cache lines
217 add r2, r2, #4 @ add 4 (line length offset)
219 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
220 clz r5, r4 @ find bit position of way size increment
222 ands r7, r7, r1, lsr #13 @ extract max number of the index size
224 mov r9, r4 @ create working copy of max way size
226 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
227 orr r11, r11, r7, lsl r2 @ factor index number into r11
228 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
229 subs r9, r9, #1 @ decrement the way
231 subs r7, r7, #1 @ decrement the index
234 add r10, r10, #2 @ increment cache number
238 mov r10, #0 @ swith back to cache level 0
239 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
241 mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
242 @ with armv7 this is 'isb',
243 @ but we compile with armv5
247 * v7_flush_cache_all()
249 * Flush the entire cache system.
250 * The data cache flush is now achieved using atomic clean / invalidates
251 * working outwards from L1 cache. This is done using Set/Way based cache
252 * maintainance instructions.
253 * The instruction cache can still be invalidated back to the point of
254 * unification in a single instruction.
258 stmfd sp!, {r0-r7, r9-r11, lr}
259 bl v7_flush_dcache_all
261 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
262 ldmfd sp!, {r0-r7, r9-r11, lr}