3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clocks_omap3.h>
19 #include <asm/arch/mem.h>
20 #include <asm/arch/sys_proto.h>
21 #include <environment.h>
24 /******************************************************************************
25 * get_sys_clk_speed() - determine reference oscillator speed
26 * based on known 32kHz clock and gptimer.
27 *****************************************************************************/
28 u32 get_osc_clk_speed(void)
30 u32 start, cstart, cend, cdiff, cdiv, val;
31 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
32 struct prm *prm_base = (struct prm *)PRM_BASE;
33 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
34 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
36 val = readl(&prm_base->clksrc_ctrl);
38 if (val & SYSCLKDIV_2)
44 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
46 /* select sys_clk for GPT1 */
47 writel(val, &prcm_base->clksel_wkup);
49 /* Enable I and F Clocks for GPT1 */
50 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
51 writel(val, &prcm_base->iclken_wkup);
53 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
54 writel(val, &prcm_base->fclken_wkup);
56 writel(0, &gpt1_base->tldr); /* start counting at 0 */
57 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
59 /* enable 32kHz source, determine sys_clk via gauging */
61 /* start time in 20 cycles */
62 start = 20 + readl(&s32k_base->s32k_cr);
64 /* dead loop till start time */
65 while (readl(&s32k_base->s32k_cr) < start);
67 /* get start sys_clk count */
68 cstart = readl(&gpt1_base->tcrr);
70 /* wait for 40 cycles */
71 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
72 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
73 cdiff = cend - cstart; /* get elapsed ticks */
76 /* based on number of ticks assign speed */
79 else if (cdiff > 15200)
81 else if (cdiff > 13000)
83 else if (cdiff > 9000)
85 else if (cdiff > 7600)
91 /******************************************************************************
92 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
93 * input oscillator clock frequency.
94 *****************************************************************************/
95 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
117 * OMAP34XX/35XX specific functions
120 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
122 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
123 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
124 void (*f_lock_pll) (u32, u32, u32, u32);
125 int xip_safe, p0, p1, p2, p3;
127 xip_safe = is_running_in_sram();
129 /* Moving to the right sysclk and ES rev base */
130 ptr = ptr + (3 * clk_index) + sil_index;
136 clrsetbits_le32(&prcm_base->clken_pll,
137 0x00000007, PLL_FAST_RELOCK_BYPASS);
138 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
142 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
143 * work. write another value and then default value.
146 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
147 clrsetbits_le32(&prcm_base->clksel1_emu,
148 0x001F0000, (CORE_M3X2 + 1) << 16) ;
149 clrsetbits_le32(&prcm_base->clksel1_emu,
150 0x001F0000, CORE_M3X2 << 16);
152 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
153 clrsetbits_le32(&prcm_base->clksel1_pll,
154 0xF8000000, ptr->m2 << 27);
156 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
157 clrsetbits_le32(&prcm_base->clksel1_pll,
158 0x07FF0000, ptr->m << 16);
160 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
161 clrsetbits_le32(&prcm_base->clksel1_pll,
162 0x00007F00, ptr->n << 8);
164 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
165 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
168 clrsetbits_le32(&prcm_base->clksel_core,
169 0x00000F00, CORE_SSI_DIV << 8);
171 clrsetbits_le32(&prcm_base->clksel_core,
172 0x00000030, CORE_FUSB_DIV << 4);
174 clrsetbits_le32(&prcm_base->clksel_core,
175 0x0000000C, CORE_L4_DIV << 2);
177 clrsetbits_le32(&prcm_base->clksel_core,
178 0x00000003, CORE_L3_DIV);
180 clrsetbits_le32(&prcm_base->clksel_gfx,
181 0x00000007, GFX_DIV);
183 clrsetbits_le32(&prcm_base->clksel_wkup,
184 0x00000006, WKUP_RSM << 1);
185 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
186 clrsetbits_le32(&prcm_base->clken_pll,
187 0x000000F0, ptr->fsel << 4);
189 clrsetbits_le32(&prcm_base->clken_pll,
190 0x00000007, PLL_LOCK);
192 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
194 } else if (is_running_in_flash()) {
196 * if running from flash, jump to small relocated code
199 f_lock_pll = (void *) (SRAM_CLK_CODE);
201 p0 = readl(&prcm_base->clken_pll);
202 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
203 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
204 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
206 p1 = readl(&prcm_base->clksel1_pll);
207 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
208 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
209 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
210 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
211 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
212 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
213 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
214 clrbits_le32(&p1, 0x00000040);
216 p2 = readl(&prcm_base->clksel_core);
218 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
220 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
222 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
224 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
226 p3 = (u32)&prcm_base->idlest_ckgen;
228 (*f_lock_pll) (p0, p1, p2, p3);
232 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
234 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
235 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
237 /* Moving it to the right sysclk base */
238 ptr = ptr + clk_index;
240 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
241 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
242 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
245 * Errata 1.50 Workaround for OMAP3 ES1.0 only
246 * If using default divisors, write default divisor + 1
247 * and then the actual divisor value
250 clrsetbits_le32(&prcm_base->clksel1_emu,
251 0x1F000000, (PER_M6X2 + 1) << 24);
252 clrsetbits_le32(&prcm_base->clksel1_emu,
253 0x1F000000, PER_M6X2 << 24);
255 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
256 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
259 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
261 clrsetbits_le32(&prcm_base->clksel_dss,
262 0x00001F00, (PER_M3X2 + 1) << 8);
263 clrsetbits_le32(&prcm_base->clksel_dss,
264 0x00001F00, PER_M3X2 << 8);
265 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
267 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
270 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
271 clrsetbits_le32(&prcm_base->clksel2_pll,
272 0x0007FF00, ptr->m << 8);
274 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
275 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
277 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
278 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
280 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
281 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
282 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
285 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
287 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
288 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
290 /* Moving it to the right sysclk base */
291 ptr = ptr + clk_index;
293 /* PER2 DPLL (DPLL5) */
294 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
295 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
296 /* set M2 (usbtll_fck) */
297 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
298 /* set m (11-bit multiplier) */
299 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
300 /* set n (7-bit divider)*/
301 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
303 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
305 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
306 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
309 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
311 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
312 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
314 /* Moving to the right sysclk and ES rev base */
315 ptr = ptr + (3 * clk_index) + sil_index;
317 /* MPU DPLL (unlocked already) */
319 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
320 clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
321 0x0000001F, ptr->m2);
323 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
324 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
325 0x0007FF00, ptr->m << 8);
327 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
328 clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
331 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
332 clrsetbits_le32(&prcm_base->clken_pll_mpu,
333 0x000000F0, ptr->fsel << 4);
336 static void iva_init_34xx(u32 sil_index, u32 clk_index)
338 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
339 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
341 /* Moving to the right sysclk and ES rev base */
342 ptr = ptr + (3 * clk_index) + sil_index;
345 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
346 clrsetbits_le32(&prcm_base->clken_pll_iva2,
347 0x00000007, PLL_STOP);
348 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
350 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
351 clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
352 0x0000001F, ptr->m2);
354 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
355 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
356 0x0007FF00, ptr->m << 8);
358 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
359 clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
362 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
363 clrsetbits_le32(&prcm_base->clken_pll_iva2,
364 0x000000F0, ptr->fsel << 4);
366 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
367 clrsetbits_le32(&prcm_base->clken_pll_iva2,
368 0x00000007, PLL_LOCK);
370 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
374 * OMAP3630 specific functions
377 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
379 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
380 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
381 void (*f_lock_pll) (u32, u32, u32, u32);
382 int xip_safe, p0, p1, p2, p3;
384 xip_safe = is_running_in_sram();
386 /* Moving it to the right sysclk base */
392 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
393 clrsetbits_le32(&prcm_base->clken_pll,
394 0x00000007, PLL_FAST_RELOCK_BYPASS);
395 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
398 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
399 clrsetbits_le32(&prcm_base->clksel1_emu,
400 0x001F0000, CORE_M3X2 << 16);
402 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
403 clrsetbits_le32(&prcm_base->clksel1_pll,
404 0xF8000000, ptr->m2 << 27);
406 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
407 clrsetbits_le32(&prcm_base->clksel1_pll,
408 0x07FF0000, ptr->m << 16);
410 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
411 clrsetbits_le32(&prcm_base->clksel1_pll,
412 0x00007F00, ptr->n << 8);
414 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
415 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
418 clrsetbits_le32(&prcm_base->clksel_core,
419 0x00000F00, CORE_SSI_DIV << 8);
421 clrsetbits_le32(&prcm_base->clksel_core,
422 0x00000030, CORE_FUSB_DIV << 4);
424 clrsetbits_le32(&prcm_base->clksel_core,
425 0x0000000C, CORE_L4_DIV << 2);
427 clrsetbits_le32(&prcm_base->clksel_core,
428 0x00000003, CORE_L3_DIV);
430 clrsetbits_le32(&prcm_base->clksel_gfx,
431 0x00000007, GFX_DIV_36X);
433 clrsetbits_le32(&prcm_base->clksel_wkup,
434 0x00000006, WKUP_RSM << 1);
435 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
436 clrsetbits_le32(&prcm_base->clken_pll,
437 0x000000F0, ptr->fsel << 4);
439 clrsetbits_le32(&prcm_base->clken_pll,
440 0x00000007, PLL_LOCK);
442 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
444 } else if (is_running_in_flash()) {
446 * if running from flash, jump to small relocated code
449 f_lock_pll = (void *) (SRAM_CLK_CODE);
451 p0 = readl(&prcm_base->clken_pll);
452 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
453 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
454 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
456 p1 = readl(&prcm_base->clksel1_pll);
457 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
458 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
459 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
460 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
461 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
462 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
463 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
464 clrbits_le32(&p1, 0x00000040);
466 p2 = readl(&prcm_base->clksel_core);
468 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
470 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
472 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
474 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
476 p3 = (u32)&prcm_base->idlest_ckgen;
478 (*f_lock_pll) (p0, p1, p2, p3);
482 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
484 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
485 struct dpll_per_36x_param *ptr;
487 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
489 /* Moving it to the right sysclk base */
492 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
493 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
494 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
496 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
497 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
499 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
500 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
502 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
503 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
505 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
506 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
508 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
509 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
511 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
512 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
514 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
515 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
517 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
518 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
520 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
521 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
522 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
525 static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
527 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
528 dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
530 /* Moving it to the right sysclk base */
531 ptr = ptr + clk_index;
533 /* PER2 DPLL (DPLL5) */
534 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
535 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
536 /* set M2 (usbtll_fck) */
537 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
538 /* set m (11-bit multiplier) */
539 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
540 /* set n (7-bit divider)*/
541 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
543 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
544 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
547 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
549 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
550 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
552 /* Moving to the right sysclk */
555 /* MPU DPLL (unlocked already */
557 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
558 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
560 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
561 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
563 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
564 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
567 static void iva_init_36xx(u32 sil_index, u32 clk_index)
569 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
570 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
572 /* Moving to the right sysclk */
576 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
577 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
578 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
580 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
581 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
583 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
584 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
586 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
587 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
589 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
590 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
592 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
595 /******************************************************************************
596 * prcm_init() - inits clocks for PRCM as defined in clocks.h
597 * called from SRAM, or Flash (using temp SRAM stack).
598 *****************************************************************************/
601 u32 osc_clk = 0, sys_clkin_sel;
602 u32 clk_index, sil_index = 0;
603 struct prm *prm_base = (struct prm *)PRM_BASE;
604 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
607 * Gauge the input clock speed and find out the sys_clkin_sel
608 * value corresponding to the input clock.
610 osc_clk = get_osc_clk_speed();
611 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
613 /* set input crystal speed */
614 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
616 /* If the input clock is greater than 19.2M always divide/2 */
617 if (sys_clkin_sel > 2) {
618 /* input clock divider */
619 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
620 clk_index = sys_clkin_sel / 2;
622 /* input clock divider */
623 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
624 clk_index = sys_clkin_sel;
627 if (get_cpu_family() == CPU_OMAP36XX) {
629 * In warm reset conditions on OMAP36xx/AM/DM37xx
630 * the rom code incorrectly sets the DPLL4 clock
631 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
632 * the AM/DM37x TRM explains that the /6.5 divider
633 * is used only when the input clock is 13MHz.
635 * If the part is in this cpu family *and* the input
636 * clock *is not* 13 MHz, then reset the DPLL4 clock
637 * input divider to /1 as it should never set to /6.5
640 if (sys_clkin_sel != 1) { /* 13 MHz */
641 /* Bit 8: DPLL4_CLKINP_DIV */
642 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
645 /* Unlock MPU DPLL (slows things down, and needed later) */
646 clrsetbits_le32(&prcm_base->clken_pll_mpu,
647 0x00000007, PLL_LOW_POWER_BYPASS);
648 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
651 dpll3_init_36xx(0, clk_index);
652 dpll4_init_36xx(0, clk_index);
653 dpll5_init_36xx(0, clk_index);
654 iva_init_36xx(0, clk_index);
655 mpu_init_36xx(0, clk_index);
657 /* Lock MPU DPLL to set frequency */
658 clrsetbits_le32(&prcm_base->clken_pll_mpu,
659 0x00000007, PLL_LOCK);
660 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
664 * The DPLL tables are defined according to sysclk value and
665 * silicon revision. The clk_index value will be used to get
666 * the values for that input sysclk from the DPLL param table
667 * and sil_index will get the values for that SysClk for the
668 * appropriate silicon rev.
670 if (((get_cpu_family() == CPU_OMAP34XX)
671 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
672 (get_cpu_family() == CPU_AM35XX))
675 /* Unlock MPU DPLL (slows things down, and needed later) */
676 clrsetbits_le32(&prcm_base->clken_pll_mpu,
677 0x00000007, PLL_LOW_POWER_BYPASS);
678 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
681 dpll3_init_34xx(sil_index, clk_index);
682 dpll4_init_34xx(sil_index, clk_index);
683 dpll5_init_34xx(sil_index, clk_index);
684 if (get_cpu_family() != CPU_AM35XX)
685 iva_init_34xx(sil_index, clk_index);
687 mpu_init_34xx(sil_index, clk_index);
689 /* Lock MPU DPLL to set frequency */
690 clrsetbits_le32(&prcm_base->clken_pll_mpu,
691 0x00000007, PLL_LOCK);
692 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
696 /* Set up GPTimers to sys_clk source only */
697 setbits_le32(&prcm_base->clksel_per, 0x000000FF);
698 setbits_le32(&prcm_base->clksel_wkup, 1);
704 * Enable usb ehci uhh, tll clocks
706 void ehci_clocks_enable(void)
708 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
710 /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
711 setbits_le32(&prcm_base->iclken_usbhost, 1);
713 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
714 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
716 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
717 /* Enable USBTTL_ICLK */
718 setbits_le32(&prcm_base->iclken3_core, 0x00000004);
719 /* Enable USBTTL_FCLK */
720 setbits_le32(&prcm_base->fclken3_core, 0x00000004);
723 /******************************************************************************
724 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
725 *****************************************************************************/
726 void per_clocks_enable(void)
728 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
730 /* Enable GP2 timer. */
731 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
732 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
733 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
735 #ifdef CONFIG_SYS_NS16550
736 /* Enable UART1 clocks */
737 setbits_le32(&prcm_base->fclken1_core, 0x00002000);
738 setbits_le32(&prcm_base->iclken1_core, 0x00002000);
741 setbits_le32(&prcm_base->fclken_per, 0x00000800);
742 setbits_le32(&prcm_base->iclken_per, 0x00000800);
745 #ifdef CONFIG_OMAP3_GPIO_2
746 setbits_le32(&prcm_base->fclken_per, 0x00002000);
747 setbits_le32(&prcm_base->iclken_per, 0x00002000);
749 #ifdef CONFIG_OMAP3_GPIO_3
750 setbits_le32(&prcm_base->fclken_per, 0x00004000);
751 setbits_le32(&prcm_base->iclken_per, 0x00004000);
753 #ifdef CONFIG_OMAP3_GPIO_4
754 setbits_le32(&prcm_base->fclken_per, 0x00008000);
755 setbits_le32(&prcm_base->iclken_per, 0x00008000);
757 #ifdef CONFIG_OMAP3_GPIO_5
758 setbits_le32(&prcm_base->fclken_per, 0x00010000);
759 setbits_le32(&prcm_base->iclken_per, 0x00010000);
761 #ifdef CONFIG_OMAP3_GPIO_6
762 setbits_le32(&prcm_base->fclken_per, 0x00020000);
763 setbits_le32(&prcm_base->iclken_per, 0x00020000);
766 #ifdef CONFIG_SYS_I2C_OMAP34XX
767 /* Turn on all 3 I2C clocks */
768 setbits_le32(&prcm_base->fclken1_core, 0x00038000);
769 setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
771 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
772 setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
774 if (get_cpu_family() != CPU_AM35XX)
775 out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
777 out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
778 out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
779 out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
780 out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
781 out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
782 out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
783 out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
784 if (get_cpu_family() != CPU_AM35XX) {
785 out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
786 out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);