3 * Vaibhav Hiremath <hvaibhav@ti.com>
5 * Based on mem.c and sdrc.c
8 * Texas Instruments Incorporated - http://www.ti.com/
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/mem.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/emif4.h>
32 DECLARE_GLOBAL_DATA_PTR;
33 extern omap3_sysinfo sysinfo;
35 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
39 * - Return 1 if mem type in use is SDR
48 * - Get size of chip select 0/1
50 u32 get_sdr_cs_size(u32 cs)
54 /* TODO: Calculate the size based on EMIF4 configuration */
56 size = CONFIG_SYS_CS0_SIZE;
63 * - Get offset of cs from cs0 start
65 u32 get_sdr_cs_offset(u32 cs)
74 * - Init the emif4 module for DDR access
75 * - Early init routines, called from flash or SRAM.
77 void do_emif4_init(void)
80 /* Set the DDR PHY parameters in PHY ctrl registers */
81 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
82 EMIF4_DDR1_EXT_STRB_DIS);
83 writel(regval, &emif4_base->ddr_phyctrl1);
84 writel(regval, &emif4_base->ddr_phyctrl1_shdw);
85 writel(0, &emif4_base->ddr_phyctrl2);
87 /* Reset the DDR PHY and wait till completed */
88 regval = readl(&emif4_base->sdram_iodft_tlgc);
90 writel(regval, &emif4_base->sdram_iodft_tlgc);
91 /*Wait till that bit clears*/
92 while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
93 /*Re-verify the DDR PHY status*/
94 while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
97 writel(regval, &emif4_base->sdram_iodft_tlgc);
98 /* Set SDR timing registers */
99 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
100 EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
101 EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
103 writel(regval, &emif4_base->sdram_time1);
104 writel(regval, &emif4_base->sdram_time1_shdw);
106 regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
107 EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
108 EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
109 writel(regval, &emif4_base->sdram_time2);
110 writel(regval, &emif4_base->sdram_time2_shdw);
112 regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
113 writel(regval, &emif4_base->sdram_time3);
114 writel(regval, &emif4_base->sdram_time3_shdw);
116 /* Set the PWR control register */
117 regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
118 EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
119 writel(regval, &emif4_base->sdram_pwr_mgmt);
120 writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
122 /* Set the DDR refresh rate control register */
123 regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
124 writel(regval, &emif4_base->sdram_refresh_ctrl);
125 writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
127 /* set the SDRAM configuration register */
128 regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
129 EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
130 EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
131 EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
132 EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
133 EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
134 writel(regval, &emif4_base->sdram_config);
139 * - Sets uboots idea of sdram size
143 unsigned int size0 = 0, size1 = 0;
145 size0 = get_sdr_cs_size(CS0);
147 * If a second bank of DDR is attached to CS1 this is
148 * where it can be started. Early init code will init
151 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
152 size1 = get_sdr_cs_size(CS1);
154 gd->ram_size = size0 + size1;
158 void dram_init_banksize (void)
160 unsigned int size0 = 0, size1 = 0;
162 size0 = get_sdr_cs_size(CS0);
163 size1 = get_sdr_cs_size(CS1);
165 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
166 gd->bd->bi_dram[0].size = size0;
167 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
168 gd->bd->bi_dram[1].size = size1;
173 * - Initialize memory subsystem