2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/mem.h>
33 #include <asm/arch/clocks_omap3.h>
36 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
38 .global omap3_gp_romcode_call
39 omap3_gp_romcode_call:
40 PUSH {r4-r12, lr} @ Save all registers from ROM code!
41 MOV r12, r0 @ Copy the Service ID in R12
42 MOV r0, r1 @ Copy parameter to R0
43 mcr p15, 0, r0, c7, c10, 4 @ DSB
44 mcr p15, 0, r0, c7, c10, 5 @ DMB
45 .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
46 @ because we use -march=armv5
50 * Funtion for making PPA HAL API calls in secure devices
55 .global do_omap3_emu_romcode_call
56 do_omap3_emu_romcode_call:
57 PUSH {r4-r12, lr} @ Save all registers from ROM code!
58 MOV r12, r0 @ Copy the Secure Service ID in R12
59 MOV r3, r1 @ Copy the pointer to va_list in R3
60 MOV r1, #0 @ Process ID - 0
61 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
63 MOV r6, #0xFF @ Indicate new Task call
64 mcr p15, 0, r0, c7, c10, 4 @ DSB
65 mcr p15, 0, r0, c7, c10, 5 @ DMB
66 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
67 @ because we use -march=armv5
70 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
71 /**************************************************************************
72 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
73 * R1 = SRAM destination address.
74 *************************************************************************/
77 /* Copy DPLL code into SRAM */
78 adr r0, go_to_speed /* get addr of clock setting code */
79 mov r2, #384 /* r2 size to copy (div by 32 bytes) */
80 mov r1, r1 /* r1 <- dest address (passed in) */
81 add r2, r2, r0 /* r2 <- source end address */
83 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
84 stmia r1!, {r3 - r10} /* copy to target address [r1] */
85 cmp r0, r2 /* until source end address [r2] */
87 mov pc, lr /* back to caller */
89 /* ***************************************************************************
90 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
91 * -executed from SRAM.
92 * R0 = CM_CLKEN_PLL-bypass value
93 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
94 * R2 = CM_CLKSEL_CORE-divider values
95 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
97 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
98 * confused. A reset of the controller gets it back. Taking away its
99 * L3 when its not in self refresh seems bad for it. Normally, this
100 * code runs from flash before SDR is init so that should be ok.
101 ****************************************************************************/
106 /* move into fast relock bypass */
110 ldr r5, [r3] /* get status */
111 and r5, r5, #0x1 /* isolate core status */
112 cmp r5, #0x1 /* still locked? */
113 beq wait1 /* if lock, loop */
115 /* set new dpll dividers _after_ in bypass */
117 str r1, [r5] /* set m, n, m2 */
119 str r2, [r5] /* set l3/l4/.. dividers*/
120 ldr r5, pll_div_add3 /* wkup */
121 ldr r2, pll_div_val3 /* rsm val */
123 ldr r5, pll_div_add4 /* gfx */
126 ldr r5, pll_div_add5 /* emu */
130 /* now prepare GPMC (flash) for new dpll speed */
131 /* flash needs to be stable when we jump back to it */
132 ldr r5, flash_cfg3_addr
133 ldr r2, flash_cfg3_val
135 ldr r5, flash_cfg4_addr
136 ldr r2, flash_cfg4_val
138 ldr r5, flash_cfg5_addr
139 ldr r2, flash_cfg5_val
141 ldr r5, flash_cfg1_addr
143 orr r2, r2, #0x3 /* up gpmc divider */
146 /* lock DPLL3 and wait a bit */
147 orr r0, r0, #0x7 /* set up for lock mode */
148 str r0, [r4] /* lock */
149 nop /* ARM slow at this point working at sys_clk */
154 ldr r5, [r3] /* get status */
155 and r5, r5, #0x1 /* isolate core status */
156 cmp r5, #0x1 /* still locked? */
157 bne wait2 /* if lock, loop */
163 mov pc, lr /* back to caller, locked */
165 _go_to_speed: .word go_to_speed
167 /* these constants need to be close for PIC code */
168 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
170 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
172 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
174 .word STNOR_GPMC_CONFIG3
176 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
178 .word STNOR_GPMC_CONFIG4
180 .word STNOR_GPMC_CONFIG5
182 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
192 .word (WKUP_RSM << 1)
207 str ip, [sp] /* stash old link register */
208 mov ip, lr /* save link reg across call */
209 bl s_init /* go setup pll, mux, memory */
210 ldr ip, [sp] /* restore save ip */
211 mov lr, ip /* restore link reg */
213 /* back to arch calling code */
216 /* the literal pools origin */
222 .word LOW_LEVEL_SRAM_STACK
224 /* DPLL(1-4) PARAM TABLES */
227 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
228 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
229 * The values are defined for all possible sysclk and for ES1 and ES2.
235 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
237 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
239 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
243 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
245 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
247 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
251 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
253 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
255 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
259 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
261 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
263 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
267 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
269 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
271 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
274 .globl get_mpu_dpll_param
276 adr r0, mpu_dpll_param
282 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
284 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
286 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
290 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
292 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
294 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
298 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
300 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
302 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
306 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
308 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
310 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
314 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
316 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
318 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
321 .globl get_iva_dpll_param
323 adr r0, iva_dpll_param
326 /* Core DPLL targets for L3 at 166 & L133 */
330 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
332 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
334 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
338 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
340 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
342 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
346 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
348 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
350 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
354 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
356 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
358 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
362 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
364 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
366 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
368 .globl get_core_dpll_param
370 adr r0, core_dpll_param
373 /* PER DPLL values are same for both ES1 and ES2 */
376 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
379 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
382 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
385 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
388 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
390 .globl get_per_dpll_param
392 adr r0, per_dpll_param
395 /* PER2 DPLL values */
398 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
401 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
404 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
407 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
410 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
412 .globl get_per2_dpll_param
414 adr r0, per2_dpll_param
418 * Tables for 36XX/37XX devices
458 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
459 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
460 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
461 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
462 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
463 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
465 .globl get_36x_mpu_dpll_param
466 get_36x_mpu_dpll_param:
467 adr r0, mpu_36x_dpll_param
470 .globl get_36x_iva_dpll_param
471 get_36x_iva_dpll_param:
472 adr r0, iva_36x_dpll_param
475 .globl get_36x_core_dpll_param
476 get_36x_core_dpll_param:
477 adr r0, core_36x_dpll_param
480 .globl get_36x_per_dpll_param
481 get_36x_per_dpll_param:
482 adr r0, per_36x_dpll_param