2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/mem.h>
17 #include <asm/arch/clocks_omap3.h>
18 #include <linux/linkage.h>
20 #ifdef CONFIG_SPL_BUILD
21 ENTRY(save_boot_params)
22 ldr r4, =omap3_boot_device
26 b save_boot_params_ret
27 ENDPROC(save_boot_params)
30 ENTRY(omap3_gp_romcode_call)
31 PUSH {r4-r12, lr} @ Save all registers from ROM code!
32 MOV r12, r0 @ Copy the Service ID in R12
33 MOV r0, r1 @ Copy parameter to R0
34 mcr p15, 0, r0, c7, c10, 4 @ DSB
35 mcr p15, 0, r0, c7, c10, 5 @ DMB
36 .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
37 @ because we use -march=armv5
39 ENDPROC(omap3_gp_romcode_call)
42 * Funtion for making PPA HAL API calls in secure devices
47 ENTRY(do_omap3_emu_romcode_call)
48 PUSH {r4-r12, lr} @ Save all registers from ROM code!
49 MOV r12, r0 @ Copy the Secure Service ID in R12
50 MOV r3, r1 @ Copy the pointer to va_list in R3
51 MOV r1, #0 @ Process ID - 0
52 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
54 MOV r6, #0xFF @ Indicate new Task call
55 mcr p15, 0, r0, c7, c10, 4 @ DSB
56 mcr p15, 0, r0, c7, c10, 5 @ DMB
57 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
58 @ because we use -march=armv5
60 ENDPROC(do_omap3_emu_romcode_call)
62 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
63 /**************************************************************************
64 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
65 * R1 = SRAM destination address.
66 *************************************************************************/
68 /* Copy DPLL code into SRAM */
69 adr r0, go_to_speed /* copy from start of go_to_speed... */
70 adr r2, lowlevel_init /* ... up to start of low_level_init */
72 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
73 stmia r1!, {r3 - r10} /* copy to target address [r1] */
74 cmp r0, r2 /* until source end address [r2] */
76 mov pc, lr /* back to caller */
79 /* ***************************************************************************
80 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
81 * -executed from SRAM.
82 * R0 = CM_CLKEN_PLL-bypass value
83 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
84 * R2 = CM_CLKSEL_CORE-divider values
85 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
87 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
88 * confused. A reset of the controller gets it back. Taking away its
89 * L3 when its not in self refresh seems bad for it. Normally, this
90 * code runs from flash before SDR is init so that should be ok.
91 ****************************************************************************/
95 /* move into fast relock bypass */
99 ldr r5, [r3] /* get status */
100 and r5, r5, #0x1 /* isolate core status */
101 cmp r5, #0x1 /* still locked? */
102 beq wait1 /* if lock, loop */
104 /* set new dpll dividers _after_ in bypass */
106 str r1, [r5] /* set m, n, m2 */
108 str r2, [r5] /* set l3/l4/.. dividers*/
109 ldr r5, pll_div_add3 /* wkup */
110 ldr r2, pll_div_val3 /* rsm val */
112 ldr r5, pll_div_add4 /* gfx */
115 ldr r5, pll_div_add5 /* emu */
119 /* now prepare GPMC (flash) for new dpll speed */
120 /* flash needs to be stable when we jump back to it */
121 ldr r5, flash_cfg3_addr
122 ldr r2, flash_cfg3_val
124 ldr r5, flash_cfg4_addr
125 ldr r2, flash_cfg4_val
127 ldr r5, flash_cfg5_addr
128 ldr r2, flash_cfg5_val
130 ldr r5, flash_cfg1_addr
132 orr r2, r2, #0x3 /* up gpmc divider */
135 /* lock DPLL3 and wait a bit */
136 orr r0, r0, #0x7 /* set up for lock mode */
137 str r0, [r4] /* lock */
138 nop /* ARM slow at this point working at sys_clk */
143 ldr r5, [r3] /* get status */
144 and r5, r5, #0x1 /* isolate core status */
145 cmp r5, #0x1 /* still locked? */
146 bne wait2 /* if lock, loop */
152 mov pc, lr /* back to caller, locked */
155 _go_to_speed: .word go_to_speed
157 /* these constants need to be close for PIC code */
158 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
160 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
162 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
164 .word STNOR_GPMC_CONFIG3
166 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
168 .word STNOR_GPMC_CONFIG4
170 .word STNOR_GPMC_CONFIG5
172 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
182 .word (WKUP_RSM << 1)
196 str ip, [sp] /* stash ip register */
197 mov ip, lr /* save link reg across call */
198 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
200 * No need to copy/exec the clock code - DPLL adjust already done
201 * in NAND/oneNAND Boot.
203 ldr r1, =SRAM_CLK_CODE
205 #endif /* NAND Boot */
206 mov lr, ip /* restore link reg */
207 ldr ip, [sp] /* restore save ip */
208 /* tail-call s_init to setup pll, mux, memory */
211 ENDPROC(lowlevel_init)
213 /* the literal pools origin */
219 .word LOW_LEVEL_SRAM_STACK
221 /* DPLL(1-4) PARAM TABLES */
224 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
225 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
226 * The values are defined for all possible sysclk and for ES1 and ES2.
232 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
234 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
236 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
240 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
242 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
244 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
248 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
250 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
252 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
256 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
258 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
260 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
264 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
266 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
268 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
271 .globl get_mpu_dpll_param
273 adr r0, mpu_dpll_param
279 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
281 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
283 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
287 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
289 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
291 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
295 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
297 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
299 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
303 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
305 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
307 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
311 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
313 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
315 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
318 .globl get_iva_dpll_param
320 adr r0, iva_dpll_param
323 /* Core DPLL targets for L3 at 166 & L133 */
327 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
329 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
331 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
335 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
337 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
339 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
343 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
345 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
347 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
351 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
353 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
355 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
359 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
361 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
363 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
365 .globl get_core_dpll_param
367 adr r0, core_dpll_param
370 /* PER DPLL values are same for both ES1 and ES2 */
373 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
376 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
379 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
382 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
385 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
387 .globl get_per_dpll_param
389 adr r0, per_dpll_param
392 /* PER2 DPLL values */
395 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
398 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
401 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
404 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
407 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
409 .globl get_per2_dpll_param
411 adr r0, per2_dpll_param
415 * Tables for 36XX/37XX devices
455 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
456 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
457 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
458 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
459 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
460 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
464 .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
466 .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
468 .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
470 .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
472 .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
475 ENTRY(get_36x_mpu_dpll_param)
476 adr r0, mpu_36x_dpll_param
478 ENDPROC(get_36x_mpu_dpll_param)
480 ENTRY(get_36x_iva_dpll_param)
481 adr r0, iva_36x_dpll_param
483 ENDPROC(get_36x_iva_dpll_param)
485 ENTRY(get_36x_core_dpll_param)
486 adr r0, core_36x_dpll_param
488 ENDPROC(get_36x_core_dpll_param)
490 ENTRY(get_36x_per_dpll_param)
491 adr r0, per_36x_dpll_param
493 ENDPROC(get_36x_per_dpll_param)
495 ENTRY(get_36x_per2_dpll_param)
496 adr r0, per2_36x_dpll_param
498 ENDPROC(get_36x_per2_dpll_param)