2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/mem.h>
33 #include <asm/arch/clocks_omap3.h>
36 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
38 .global save_boot_params
40 #ifdef CONFIG_SPL_BUILD
41 ldr r4, =omap3_boot_device
48 .global omap3_gp_romcode_call
49 omap3_gp_romcode_call:
50 PUSH {r4-r12, lr} @ Save all registers from ROM code!
51 MOV r12, r0 @ Copy the Service ID in R12
52 MOV r0, r1 @ Copy parameter to R0
53 mcr p15, 0, r0, c7, c10, 4 @ DSB
54 mcr p15, 0, r0, c7, c10, 5 @ DMB
55 .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
56 @ because we use -march=armv5
60 * Funtion for making PPA HAL API calls in secure devices
65 .global do_omap3_emu_romcode_call
66 do_omap3_emu_romcode_call:
67 PUSH {r4-r12, lr} @ Save all registers from ROM code!
68 MOV r12, r0 @ Copy the Secure Service ID in R12
69 MOV r3, r1 @ Copy the pointer to va_list in R3
70 MOV r1, #0 @ Process ID - 0
71 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
73 MOV r6, #0xFF @ Indicate new Task call
74 mcr p15, 0, r0, c7, c10, 4 @ DSB
75 mcr p15, 0, r0, c7, c10, 5 @ DMB
76 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
77 @ because we use -march=armv5
80 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
81 /**************************************************************************
82 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
83 * R1 = SRAM destination address.
84 *************************************************************************/
87 /* Copy DPLL code into SRAM */
88 adr r0, go_to_speed /* get addr of clock setting code */
89 mov r2, #384 /* r2 size to copy (div by 32 bytes) */
90 mov r1, r1 /* r1 <- dest address (passed in) */
91 add r2, r2, r0 /* r2 <- source end address */
93 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
94 stmia r1!, {r3 - r10} /* copy to target address [r1] */
95 cmp r0, r2 /* until source end address [r2] */
97 mov pc, lr /* back to caller */
99 /* ***************************************************************************
100 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
101 * -executed from SRAM.
102 * R0 = CM_CLKEN_PLL-bypass value
103 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
104 * R2 = CM_CLKSEL_CORE-divider values
105 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
107 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
108 * confused. A reset of the controller gets it back. Taking away its
109 * L3 when its not in self refresh seems bad for it. Normally, this
110 * code runs from flash before SDR is init so that should be ok.
111 ****************************************************************************/
116 /* move into fast relock bypass */
120 ldr r5, [r3] /* get status */
121 and r5, r5, #0x1 /* isolate core status */
122 cmp r5, #0x1 /* still locked? */
123 beq wait1 /* if lock, loop */
125 /* set new dpll dividers _after_ in bypass */
127 str r1, [r5] /* set m, n, m2 */
129 str r2, [r5] /* set l3/l4/.. dividers*/
130 ldr r5, pll_div_add3 /* wkup */
131 ldr r2, pll_div_val3 /* rsm val */
133 ldr r5, pll_div_add4 /* gfx */
136 ldr r5, pll_div_add5 /* emu */
140 /* now prepare GPMC (flash) for new dpll speed */
141 /* flash needs to be stable when we jump back to it */
142 ldr r5, flash_cfg3_addr
143 ldr r2, flash_cfg3_val
145 ldr r5, flash_cfg4_addr
146 ldr r2, flash_cfg4_val
148 ldr r5, flash_cfg5_addr
149 ldr r2, flash_cfg5_val
151 ldr r5, flash_cfg1_addr
153 orr r2, r2, #0x3 /* up gpmc divider */
156 /* lock DPLL3 and wait a bit */
157 orr r0, r0, #0x7 /* set up for lock mode */
158 str r0, [r4] /* lock */
159 nop /* ARM slow at this point working at sys_clk */
164 ldr r5, [r3] /* get status */
165 and r5, r5, #0x1 /* isolate core status */
166 cmp r5, #0x1 /* still locked? */
167 bne wait2 /* if lock, loop */
173 mov pc, lr /* back to caller, locked */
175 _go_to_speed: .word go_to_speed
177 /* these constants need to be close for PIC code */
178 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
180 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
182 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
184 .word STNOR_GPMC_CONFIG3
186 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
188 .word STNOR_GPMC_CONFIG4
190 .word STNOR_GPMC_CONFIG5
192 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
202 .word (WKUP_RSM << 1)
217 str ip, [sp] /* stash old link register */
218 mov ip, lr /* save link reg across call */
219 bl s_init /* go setup pll, mux, memory */
220 ldr ip, [sp] /* restore save ip */
221 mov lr, ip /* restore link reg */
223 /* back to arch calling code */
226 /* the literal pools origin */
232 .word LOW_LEVEL_SRAM_STACK
234 /* DPLL(1-4) PARAM TABLES */
237 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
238 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
239 * The values are defined for all possible sysclk and for ES1 and ES2.
245 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
247 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
249 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
253 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
255 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
257 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
261 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
263 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
265 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
269 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
271 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
273 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
277 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
279 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
281 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
284 .globl get_mpu_dpll_param
286 adr r0, mpu_dpll_param
292 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
294 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
296 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
300 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
302 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
304 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
308 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
310 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
312 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
316 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
318 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
320 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
324 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
326 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
328 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
331 .globl get_iva_dpll_param
333 adr r0, iva_dpll_param
336 /* Core DPLL targets for L3 at 166 & L133 */
340 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
342 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
344 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
348 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
350 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
352 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
356 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
358 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
360 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
364 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
366 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
368 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
372 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
374 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
376 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
378 .globl get_core_dpll_param
380 adr r0, core_dpll_param
383 /* PER DPLL values are same for both ES1 and ES2 */
386 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
389 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
392 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
395 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
398 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
400 .globl get_per_dpll_param
402 adr r0, per_dpll_param
405 /* PER2 DPLL values */
408 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
411 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
414 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
417 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
420 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
422 .globl get_per2_dpll_param
424 adr r0, per2_dpll_param
428 * Tables for 36XX/37XX devices
468 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
469 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
470 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
471 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
472 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
473 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
475 .globl get_36x_mpu_dpll_param
476 get_36x_mpu_dpll_param:
477 adr r0, mpu_36x_dpll_param
480 .globl get_36x_iva_dpll_param
481 get_36x_iva_dpll_param:
482 adr r0, iva_36x_dpll_param
485 .globl get_36x_core_dpll_param
486 get_36x_core_dpll_param:
487 adr r0, core_36x_dpll_param
490 .globl get_36x_per_dpll_param
491 get_36x_per_dpll_param:
492 adr r0, per_36x_dpll_param