3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/mem.h>
18 #include <asm/arch/sys_proto.h>
21 struct gpmc *gpmc_cfg;
23 #if defined(CONFIG_CMD_NAND)
24 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
30 M_NAND_GPMC_CONFIG6, 0
32 #endif /* CONFIG_CMD_NAND */
34 #if defined(CONFIG_CMD_ONENAND)
35 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
41 ONENAND_GPMC_CONFIG6, 0
43 #endif /* CONFIG_CMD_ONENAND */
45 /********************************************************
46 * mem_ok() - test used to see if timings are correct
47 * for a part. Helps in guessing which part
48 * we are currently using.
49 *******************************************************/
53 u32 pattern = 0x12345678;
55 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
57 writel(0x0, addr + 0x400); /* clear pos A */
58 writel(pattern, addr); /* pattern to pos B */
59 writel(0x0, addr + 4); /* remove pattern off the bus */
60 val1 = readl(addr + 0x400); /* get pos A value */
61 val2 = readl(addr); /* get val2 */
62 writel(0x0, addr + 0x400); /* clear pos A */
64 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
70 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
73 writel(0, &cs->config7);
75 /* Delay for settling */
76 writel(gpmc_config[0], &cs->config1);
77 writel(gpmc_config[1], &cs->config2);
78 writel(gpmc_config[2], &cs->config3);
79 writel(gpmc_config[3], &cs->config4);
80 writel(gpmc_config[4], &cs->config5);
81 writel(gpmc_config[5], &cs->config6);
84 * Enable the config. size is the CS size and goes in
85 * bits 11:8. We set bit 6 to enable this CS and the base
86 * address goes into bits 5:0.
88 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
89 ((base >> 24) & GPMC_BASEADDR_MASK),
94 /*****************************************************
95 * gpmc_init(): init gpmc bus
96 * Init GPMC for x16, MuxMode (SDRAM in x32).
97 * This code can only be executed from SRAM or SDRAM.
98 *****************************************************/
101 /* putting a blanket check on GPMC based on ZeBu for now */
102 gpmc_cfg = (struct gpmc *)GPMC_BASE;
103 #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
104 const u32 *gpmc_config = NULL;
110 /* global settings */
111 writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
112 writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
114 config = readl(&gpmc_cfg->config);
116 writel(config, &gpmc_cfg->config);
119 * Disable the GPMC0 config set by ROM code
120 * It conflicts with our MPDB (both at 0x08000000)
122 writel(0, &gpmc_cfg->cs[0].config7);
125 #if defined(CONFIG_CMD_NAND) /* CS 0 */
126 gpmc_config = gpmc_m_nand;
128 base = PISMO1_NAND_BASE;
129 size = PISMO1_NAND_SIZE;
130 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
133 #if defined(CONFIG_CMD_ONENAND)
134 gpmc_config = gpmc_onenand;
135 base = PISMO1_ONEN_BASE;
136 size = PISMO1_ONEN_SIZE;
137 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);