3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/mem.h>
31 #include <asm/arch/sys_proto.h>
34 struct gpmc *gpmc_cfg;
36 #if defined(CONFIG_CMD_NAND)
37 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
43 M_NAND_GPMC_CONFIG6, 0
45 #endif /* CONFIG_CMD_NAND */
47 #if defined(CONFIG_CMD_ONENAND)
48 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
54 ONENAND_GPMC_CONFIG6, 0
56 #endif /* CONFIG_CMD_ONENAND */
58 /********************************************************
59 * mem_ok() - test used to see if timings are correct
60 * for a part. Helps in guessing which part
61 * we are currently using.
62 *******************************************************/
66 u32 pattern = 0x12345678;
68 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
70 writel(0x0, addr + 0x400); /* clear pos A */
71 writel(pattern, addr); /* pattern to pos B */
72 writel(0x0, addr + 4); /* remove pattern off the bus */
73 val1 = readl(addr + 0x400); /* get pos A value */
74 val2 = readl(addr); /* get val2 */
75 writel(0x0, addr + 0x400); /* clear pos A */
77 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
83 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
86 writel(0, &cs->config7);
88 /* Delay for settling */
89 writel(gpmc_config[0], &cs->config1);
90 writel(gpmc_config[1], &cs->config2);
91 writel(gpmc_config[2], &cs->config3);
92 writel(gpmc_config[3], &cs->config4);
93 writel(gpmc_config[4], &cs->config5);
94 writel(gpmc_config[5], &cs->config6);
97 * Enable the config. size is the CS size and goes in
98 * bits 11:8. We set bit 6 to enable this CS and the base
99 * address goes into bits 5:0.
101 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
102 ((base >> 24) & GPMC_BASEADDR_MASK),
107 /*****************************************************
108 * gpmc_init(): init gpmc bus
109 * Init GPMC for x16, MuxMode (SDRAM in x32).
110 * This code can only be executed from SRAM or SDRAM.
111 *****************************************************/
114 /* putting a blanket check on GPMC based on ZeBu for now */
115 gpmc_cfg = (struct gpmc *)GPMC_BASE;
116 #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
117 const u32 *gpmc_config = NULL;
123 /* global settings */
124 writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
125 writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
127 config = readl(&gpmc_cfg->config);
129 writel(config, &gpmc_cfg->config);
132 * Disable the GPMC0 config set by ROM code
133 * It conflicts with our MPDB (both at 0x08000000)
135 writel(0, &gpmc_cfg->cs[0].config7);
138 #if defined(CONFIG_CMD_NAND) /* CS 0 */
139 gpmc_config = gpmc_m_nand;
141 base = PISMO1_NAND_BASE;
142 size = PISMO1_NAND_SIZE;
143 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
146 #if defined(CONFIG_CMD_ONENAND)
147 gpmc_config = gpmc_onenand;
148 base = PISMO1_ONEN_BASE;
149 size = PISMO1_ONEN_SIZE;
150 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);