3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/mem.h>
18 #include <asm/arch/sys_proto.h>
21 struct gpmc *gpmc_cfg;
23 #if defined(CONFIG_CMD_NAND)
24 #if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
25 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
35 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
41 M_NAND_GPMC_CONFIG6, 0
44 #endif /* CONFIG_CMD_NAND */
46 #if defined(CONFIG_CMD_ONENAND)
47 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
53 ONENAND_GPMC_CONFIG6, 0
55 #endif /* CONFIG_CMD_ONENAND */
57 /********************************************************
58 * mem_ok() - test used to see if timings are correct
59 * for a part. Helps in guessing which part
60 * we are currently using.
61 *******************************************************/
65 u32 pattern = 0x12345678;
67 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
69 writel(0x0, addr + 0x400); /* clear pos A */
70 writel(pattern, addr); /* pattern to pos B */
71 writel(0x0, addr + 4); /* remove pattern off the bus */
72 val1 = readl(addr + 0x400); /* get pos A value */
73 val2 = readl(addr); /* get val2 */
74 writel(0x0, addr + 0x400); /* clear pos A */
76 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
82 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
85 writel(0, &cs->config7);
87 /* Delay for settling */
88 writel(gpmc_config[0], &cs->config1);
89 writel(gpmc_config[1], &cs->config2);
90 writel(gpmc_config[2], &cs->config3);
91 writel(gpmc_config[3], &cs->config4);
92 writel(gpmc_config[4], &cs->config5);
93 writel(gpmc_config[5], &cs->config6);
96 * Enable the config. size is the CS size and goes in
97 * bits 11:8. We set bit 6 to enable this CS and the base
98 * address goes into bits 5:0.
100 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
101 ((base >> 24) & GPMC_BASEADDR_MASK),
106 /*****************************************************
107 * gpmc_init(): init gpmc bus
108 * Init GPMC for x16, MuxMode (SDRAM in x32).
109 * This code can only be executed from SRAM or SDRAM.
110 *****************************************************/
113 /* putting a blanket check on GPMC based on ZeBu for now */
114 gpmc_cfg = (struct gpmc *)GPMC_BASE;
115 #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
116 const u32 *gpmc_config = NULL;
122 /* global settings */
123 writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
124 writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
126 config = readl(&gpmc_cfg->config);
128 writel(config, &gpmc_cfg->config);
131 * Disable the GPMC0 config set by ROM code
132 * It conflicts with our MPDB (both at 0x08000000)
134 writel(0, &gpmc_cfg->cs[0].config7);
137 #if defined(CONFIG_CMD_NAND) /* CS 0 */
138 gpmc_config = gpmc_m_nand;
140 base = PISMO1_NAND_BASE;
141 size = PISMO1_NAND_SIZE;
142 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
145 #if defined(CONFIG_CMD_ONENAND)
146 gpmc_config = gpmc_onenand;
147 base = PISMO1_ONEN_BASE;
148 size = PISMO1_ONEN_SIZE;
149 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);