2 * Functions related to OMAP3 SDRC.
4 * This file has been created after exctracting and consolidating
5 * the SDRC related content from mem.c and board.c, also created
6 * generic init function (mem_init).
8 * Copyright (C) 2004-2010
9 * Texas Instruments Incorporated - http://www.ti.com/
12 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
15 * Vaibhav Hiremath <hvaibhav@ti.com>
17 * Original implementation by (mem.c, board.c) :
18 * Sunil Kumar <sunilsaini05@gmail.com>
19 * Shashi Ranjan <shashiranjanmca05@gmail.com>
20 * Manikandan Pillai <mani.pillai@ti.com>
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 #include <asm/arch/mem.h>
41 #include <asm/arch/sys_proto.h>
43 DECLARE_GLOBAL_DATA_PTR;
44 extern omap3_sysinfo sysinfo;
46 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
50 * - Return 1 if mem type in use is SDR
54 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
60 * make_cs1_contiguous -
61 * - For es2 and above remap cs1 behind cs0 to allow command line
62 * mem=xyz use all memory with out discontinuous support compiled in.
63 * Could do it at the ATAG, but there really is two banks...
64 * - Called as part of 2nd phase DDR init.
66 void make_cs1_contiguous(void)
68 u32 size, a_add_low, a_add_high;
70 size = get_sdr_cs_size(CS0);
71 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
72 a_add_high = (size & 3) << 8; /* set up low field */
73 a_add_low = (size & 0x3C) >> 2; /* set up high field */
74 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
81 * - Get size of chip select 0/1
83 u32 get_sdr_cs_size(u32 cs)
87 /* get ram size field */
88 size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
89 size &= 0x3FF; /* remove unwanted bits */
90 size <<= 21; /* multiply by 2 MiB to find size in MB */
96 * - Get offset of cs from cs0 start
98 u32 get_sdr_cs_offset(u32 cs)
105 offset = readl(&sdrc_base->cs_cfg);
106 offset = (offset & 15) << 27 | (offset & 0x30) << 17;
113 * - Initialize the SDRAM for use.
114 * - code called once in C-Stack only context for CS0 and a possible 2nd
115 * time depending on memory configuration from stack+global context
117 void do_sdrc_init(u32 cs, u32 early)
119 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
122 /* reset sdrc controller */
123 writel(SOFTRESET, &sdrc_base->sysconfig);
124 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
126 writel(0, &sdrc_base->sysconfig);
128 /* setup sdrc to ball mux */
129 writel(SDRC_SHARING, &sdrc_base->sharing);
131 /* Disable Power Down of CKE cuz of 1 CKE on combo part */
132 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
135 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
139 /* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
140 * to prevent this to be build in non-SPL build */
141 #ifdef CONFIG_SPL_BUILD
142 /* If we use a SPL there is no x-loader nor config header so we have
143 * to do the job ourselfs
146 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
148 /* General SDRC config */
149 writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
150 writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
153 writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
154 writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
157 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
158 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
159 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
160 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
162 writel(V_MR, &sdrc_base->cs[cs].mr);
167 * SDRC timings are set up by x-load or config header
168 * We don't need to redo them here.
169 * Older x-loads configure only CS0
170 * configure CS1 to handle this ommission
173 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
174 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
175 writel(readl(&sdrc_base->cs[CS0].mcfg),
176 &sdrc_base->cs[CS1].mcfg);
177 writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
178 &sdrc_base->cs[CS1].rfr_ctrl);
179 writel(readl(&sdrc_actim_base0->ctrla),
180 &sdrc_actim_base1->ctrla);
181 writel(readl(&sdrc_actim_base0->ctrlb),
182 &sdrc_actim_base1->ctrlb);
184 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
185 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
186 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
187 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
188 writel(readl(&sdrc_base->cs[CS0].mr),
189 &sdrc_base->cs[CS1].mr);
193 * Test ram in this bank
194 * Disable if bad or not present
197 writel(0, &sdrc_base->cs[cs].mcfg);
202 * - Sets uboots idea of sdram size
206 unsigned int size0 = 0, size1 = 0;
208 size0 = get_sdr_cs_size(CS0);
210 * If a second bank of DDR is attached to CS1 this is
211 * where it can be started. Early init code will init
214 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
215 do_sdrc_init(CS1, NOT_EARLY);
216 make_cs1_contiguous();
218 size1 = get_sdr_cs_size(CS1);
220 gd->ram_size = size0 + size1;
225 void dram_init_banksize (void)
227 unsigned int size0 = 0, size1 = 0;
229 size0 = get_sdr_cs_size(CS0);
230 size1 = get_sdr_cs_size(CS1);
232 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
233 gd->bd->bi_dram[0].size = size0;
234 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
235 gd->bd->bi_dram[1].size = size1;
240 * - Init the sdrc chip,
241 * - Selects CS0 and CS1,
245 /* only init up first bank here */
246 do_sdrc_init(CS0, EARLY_INIT);