2 * Functions related to OMAP3 SDRC.
4 * This file has been created after exctracting and consolidating
5 * the SDRC related content from mem.c and board.c, also created
6 * generic init function (mem_init).
8 * Copyright (C) 2004-2010
9 * Texas Instruments Incorporated - http://www.ti.com/
12 * Vaibhav Hiremath <hvaibhav@ti.com>
14 * Original implementation by (mem.c, board.c) :
15 * Sunil Kumar <sunilsaini05@gmail.com>
16 * Shashi Ranjan <shashiranjanmca05@gmail.com>
17 * Manikandan Pillai <mani.pillai@ti.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/mem.h>
38 #include <asm/arch/sys_proto.h>
40 DECLARE_GLOBAL_DATA_PTR;
41 extern omap3_sysinfo sysinfo;
43 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
47 * - Return 1 if mem type in use is SDR
51 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
57 * make_cs1_contiguous -
58 * - For es2 and above remap cs1 behind cs0 to allow command line
59 * mem=xyz use all memory with out discontinuous support compiled in.
60 * Could do it at the ATAG, but there really is two banks...
61 * - Called as part of 2nd phase DDR init.
63 void make_cs1_contiguous(void)
65 u32 size, a_add_low, a_add_high;
67 size = get_sdr_cs_size(CS0);
68 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
69 a_add_high = (size & 3) << 8; /* set up low field */
70 a_add_low = (size & 0x3C) >> 2; /* set up high field */
71 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
78 * - Get size of chip select 0/1
80 u32 get_sdr_cs_size(u32 cs)
84 /* get ram size field */
85 size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
86 size &= 0x3FF; /* remove unwanted bits */
87 size <<= 21; /* multiply by 2 MiB to find size in MB */
93 * - Get offset of cs from cs0 start
95 u32 get_sdr_cs_offset(u32 cs)
102 offset = readl(&sdrc_base->cs_cfg);
103 offset = (offset & 15) << 27 | (offset & 0x30) << 17;
110 * - Initialize the SDRAM for use.
111 * - code called once in C-Stack only context for CS0 and a possible 2nd
112 * time depending on memory configuration from stack+global context
114 void do_sdrc_init(u32 cs, u32 early)
116 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
119 /* reset sdrc controller */
120 writel(SOFTRESET, &sdrc_base->sysconfig);
121 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
123 writel(0, &sdrc_base->sysconfig);
125 /* setup sdrc to ball mux */
126 writel(SDRC_SHARING, &sdrc_base->sharing);
128 /* Disable Power Down of CKE cuz of 1 CKE on combo part */
129 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
132 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
137 * SDRC timings are set up by x-load or config header
138 * We don't need to redo them here.
139 * Older x-loads configure only CS0
140 * configure CS1 to handle this ommission
143 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
144 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
145 writel(readl(&sdrc_base->cs[CS0].mcfg),
146 &sdrc_base->cs[CS1].mcfg);
147 writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
148 &sdrc_base->cs[CS1].rfr_ctrl);
149 writel(readl(&sdrc_actim_base0->ctrla),
150 &sdrc_actim_base1->ctrla);
151 writel(readl(&sdrc_actim_base0->ctrlb),
152 &sdrc_actim_base1->ctrlb);
154 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
155 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
156 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
157 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
158 writel(readl(&sdrc_base->cs[CS0].mr),
159 &sdrc_base->cs[CS1].mr);
163 * Test ram in this bank
164 * Disable if bad or not present
167 writel(0, &sdrc_base->cs[cs].mcfg);
172 * - Sets uboots idea of sdram size
176 unsigned int size0 = 0, size1 = 0;
178 size0 = get_sdr_cs_size(CS0);
180 * If a second bank of DDR is attached to CS1 this is
181 * where it can be started. Early init code will init
184 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
185 do_sdrc_init(CS1, NOT_EARLY);
186 make_cs1_contiguous();
188 size1 = get_sdr_cs_size(CS1);
190 gd->ram_size = size0 + size1;
195 void dram_init_banksize (void)
197 unsigned int size0 = 0, size1 = 0;
199 size0 = get_sdr_cs_size(CS0);
200 size1 = get_sdr_cs_size(CS1);
202 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
203 gd->bd->bi_dram[0].size = size0;
204 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
205 gd->bd->bi_dram[1].size = size1;
210 * - Init the sdrc chip,
211 * - Selects CS0 and CS1,
215 /* only init up first bank here */
216 do_sdrc_init(CS0, EARLY_INIT);