2 * Functions related to OMAP3 SDRC.
4 * This file has been created after exctracting and consolidating
5 * the SDRC related content from mem.c and board.c, also created
6 * generic init function (mem_init).
8 * Copyright (C) 2004-2010
9 * Texas Instruments Incorporated - http://www.ti.com/
12 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
15 * Vaibhav Hiremath <hvaibhav@ti.com>
17 * Original implementation by (mem.c, board.c) :
18 * Sunil Kumar <sunilsaini05@gmail.com>
19 * Shashi Ranjan <shashiranjanmca05@gmail.com>
20 * Manikandan Pillai <mani.pillai@ti.com>
22 * SPDX-License-Identifier: GPL-2.0+
27 #include <asm/arch/mem.h>
28 #include <asm/arch/sys_proto.h>
30 DECLARE_GLOBAL_DATA_PTR;
31 extern omap3_sysinfo sysinfo;
33 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
37 * - Return 1 if mem type in use is SDR
41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
47 * make_cs1_contiguous -
48 * - When we have CS1 populated we want to have it mapped after cs0 to allow
49 * command line mem=xyz use all memory with out discontinuous support
50 * compiled in. We could do it in the ATAG, but there really is two banks...
52 void make_cs1_contiguous(void)
54 u32 size, a_add_low, a_add_high;
56 size = get_sdr_cs_size(CS0);
57 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
58 a_add_high = (size & 3) << 8; /* set up low field */
59 a_add_low = (size & 0x3C) >> 2; /* set up high field */
60 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
67 * - Get size of chip select 0/1
69 u32 get_sdr_cs_size(u32 cs)
73 /* get ram size field */
74 size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
75 size &= 0x3FF; /* remove unwanted bits */
76 size <<= 21; /* multiply by 2 MiB to find size in MB */
82 * - Get offset of cs from cs0 start
84 u32 get_sdr_cs_offset(u32 cs)
91 offset = readl(&sdrc_base->cs_cfg);
92 offset = (offset & 15) << 27 | (offset & 0x300) << 17;
98 * write_sdrc_timings -
99 * - Takes CS and associated timings and initalize SDRAM
100 * - Test CS to make sure it's OK for use
102 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
103 struct board_sdrc_timings *timings)
105 /* Setup timings we got from the board. */
106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
107 writel(timings->ctrla, &sdrc_actim_base->ctrla);
108 writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
109 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
110 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
111 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
112 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
113 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
114 writel(timings->mr, &sdrc_base->cs[cs].mr);
117 * Test ram in this bank
118 * Disable if bad or not present
121 writel(0, &sdrc_base->cs[cs].mcfg);
126 * - Code called once in C-Stack only context for CS0 and with early being
127 * true and a possible 2nd time depending on memory configuration from
128 * stack+global context.
130 void do_sdrc_init(u32 cs, u32 early)
132 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
133 struct board_sdrc_timings timings;
135 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
136 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
139 * When called in the early context this may be SPL and we will
140 * need to set all of the timings. This ends up being board
141 * specific so we call a helper function to take care of this
142 * for us. Otherwise, to be safe, we need to copy the settings
143 * from the first bank to the second. We will setup CS0,
144 * then set cs_cfg to the appropriate value then try and
147 #ifdef CONFIG_SPL_BUILD
148 get_board_mem_timings(&timings);
151 /* reset sdrc controller */
152 writel(SOFTRESET, &sdrc_base->sysconfig);
153 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
155 writel(0, &sdrc_base->sysconfig);
157 /* setup sdrc to ball mux */
158 writel(SDRC_SHARING, &sdrc_base->sharing);
160 /* Disable Power Down of CKE because of 1 CKE on combo part */
161 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
164 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
166 #ifdef CONFIG_SPL_BUILD
167 write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
168 make_cs1_contiguous();
169 write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
175 * If we aren't using SPL we have been loaded by some
176 * other means which may not have correctly initialized
177 * both CS0 and CS1 (such as some older versions of x-loader)
178 * so we may be asked now to setup CS1.
181 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
182 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
183 timings.ctrla = readl(&sdrc_actim_base0->ctrla);
184 timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
185 timings.mr = readl(&sdrc_base->cs[CS0].mr);
186 write_sdrc_timings(cs, sdrc_actim_base1, &timings);
192 * - Sets uboots idea of sdram size
196 unsigned int size0 = 0, size1 = 0;
198 size0 = get_sdr_cs_size(CS0);
200 * We always need to have cs_cfg point at where the second
201 * bank would be, if present. Failure to do so can lead to
202 * strange situations where memory isn't detected and
203 * configured correctly. CS0 will already have been setup
206 make_cs1_contiguous();
207 do_sdrc_init(CS1, NOT_EARLY);
208 size1 = get_sdr_cs_size(CS1);
210 gd->ram_size = size0 + size1;
215 void dram_init_banksize (void)
217 unsigned int size0 = 0, size1 = 0;
219 size0 = get_sdr_cs_size(CS0);
220 size1 = get_sdr_cs_size(CS1);
222 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
223 gd->bd->bi_dram[0].size = size0;
224 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
225 gd->bd->bi_dram[1].size = size1;
230 * - Init the sdrc chip,
231 * - Selects CS0 and CS1,
235 /* only init up first bank here */
236 do_sdrc_init(CS0, EARLY_INIT);