3 * Texas Instruments, <www.ti.com>
6 * Tom Rini <trini@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Jian Zhang <jzhang@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <linux/mtd/nand.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/mem.h>
34 static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
36 /* nand_command: Send a flash command to the flash chip */
37 static void nand_command(u8 command)
39 writeb(command, &gpmc_config->cs[0].nand_cmd);
41 if (command == NAND_CMD_RESET) {
42 unsigned char ret_val;
43 writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
45 /* Wait until ready */
46 ret_val = readl(&gpmc_config->cs[0].nand_dat);
47 } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
52 * Many boards will want to know the results of the NAND_CMD_READID command
53 * in order to decide what to do about DDR initialization. This function
54 * allows us to do that very early and to pass those results back to the
55 * board so it can make whatever decisions need to be made.
57 void identify_nand_chip(int *mfr, int *id)
59 /* Make sure that we have setup GPMC for NAND correctly. */
60 writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
61 writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
62 writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
63 writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
64 writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
65 writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
68 * Enable the config. The CS size goes in bits 11:8. We set
69 * bit 6 to enable the CS and the base address goes into bits 5:0.
71 writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
72 ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
73 &gpmc_config->cs[0].config7);
77 /* Issue a RESET and then READID */
78 nand_command(NAND_CMD_RESET);
79 nand_command(NAND_CMD_READID);
81 /* Set the address to read to 0x0 */
82 writeb(0x0, &gpmc_config->cs[0].nand_adr);
84 /* Read off the manufacturer and device id. */
85 *mfr = readb(&gpmc_config->cs[0].nand_dat);
86 *id = readb(&gpmc_config->cs[0].nand_dat);