3 * Common functions for OMAP4 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/armv7.h>
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/sizes.h>
35 #include <asm/arch/emif.h>
36 #include "omap4_mux_data.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
42 #ifdef CONFIG_SPL_BUILD
44 * We use static variables because global data is not ready yet.
45 * Initialized data is available in SPL right from the beginning.
46 * We would not typically need to save these parameters in regular
47 * U-Boot. This is needed only in SPL at the moment.
49 u32 omap4_boot_device = BOOT_DEVICE_MMC1;
50 u32 omap4_boot_mode = MMCSD_MODE_FAT;
52 u32 omap_boot_device(void)
54 return omap4_boot_device;
57 u32 omap_boot_mode(void)
59 return omap4_boot_mode;
63 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
66 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
68 for (i = 0; i < size; i++, pad++)
69 writew(pad->val, base + pad->offset);
72 static void set_muxconf_regs_essential(void)
74 do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
75 sizeof(core_padconf_array_essential) /
76 sizeof(struct pad_conf_entry));
78 do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
79 sizeof(wkup_padconf_array_essential) /
80 sizeof(struct pad_conf_entry));
83 static void set_mux_conf_regs(void)
85 switch (omap4_hw_init_context()) {
86 case OMAP_INIT_CONTEXT_SPL:
87 set_muxconf_regs_essential();
89 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
90 set_muxconf_regs_non_essential();
92 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
93 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
94 set_muxconf_regs_essential();
95 set_muxconf_regs_non_essential();
100 static u32 cortex_a9_rev(void)
105 /* Read Main ID Register (MIDR) */
106 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
111 static void init_omap4_revision(void)
114 * For some of the ES2/ES1 boards ID_CODE is not reliable:
115 * Also, ES1 and ES2 have different ARM revisions
116 * So use ARM revision for identification
118 unsigned int arm_rev = cortex_a9_rev();
121 case MIDR_CORTEX_A9_R0P1:
122 *omap4_revision = OMAP4430_ES1_0;
124 case MIDR_CORTEX_A9_R1P2:
125 switch (readl(CONTROL_ID_CODE)) {
126 case OMAP4_CONTROL_ID_CODE_ES2_0:
127 *omap4_revision = OMAP4430_ES2_0;
129 case OMAP4_CONTROL_ID_CODE_ES2_1:
130 *omap4_revision = OMAP4430_ES2_1;
132 case OMAP4_CONTROL_ID_CODE_ES2_2:
133 *omap4_revision = OMAP4430_ES2_2;
136 *omap4_revision = OMAP4430_ES2_0;
140 case MIDR_CORTEX_A9_R1P3:
141 *omap4_revision = OMAP4430_ES2_3;
143 case MIDR_CORTEX_A9_R2P10:
144 *omap4_revision = OMAP4460_ES1_0;
147 *omap4_revision = OMAP4430_SILICON_ID_INVALID;
152 void omap_rev_string(char *omap4_rev_string)
154 u32 omap4_rev = omap_revision();
155 u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
156 u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
157 u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
159 sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
165 * Description: Does early system init of watchdog, muxing, andclocks
166 * Watchdog disable is done always. For the rest what gets done
167 * depends on the boot mode in which this function is executed
168 * 1. s_init of SPL running from SRAM
169 * 2. s_init of U-Boot running from FLASH
170 * 3. s_init of U-Boot loaded to SDRAM by SPL
171 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
172 * Configuration Header feature
173 * Please have a look at the respective functions to see what gets
174 * done in each of these cases
175 * This function is called with SRAM stack.
179 init_omap4_revision();
182 #ifdef CONFIG_SPL_BUILD
183 preloader_console_init();
186 #ifdef CONFIG_SPL_BUILD
187 /* For regular u-boot sdram_init() is called from dram_init() */
193 * Routine: wait_for_command_complete
194 * Description: Wait for posting to finish on watchdog
196 void wait_for_command_complete(struct watchdog *wd_base)
200 pending = readl(&wd_base->wwps);
205 * Routine: watchdog_init
206 * Description: Shut down watch dogs
208 void watchdog_init(void)
210 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
212 writel(WD_UNLOCK1, &wd2_base->wspr);
213 wait_for_command_complete(wd2_base);
214 writel(WD_UNLOCK2, &wd2_base->wspr);
219 * This function finds the SDRAM size available in the system
220 * based on DMM section configurations
221 * This is needed because the size of memory installed may be
222 * different on different versions of the board
224 u32 omap4_sdram_size(void)
226 u32 section, i, total_size = 0, size, addr;
227 for (i = 0; i < 4; i++) {
228 section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
229 addr = section & OMAP44XX_SYS_ADDR_MASK;
230 /* See if the address is valid */
231 if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
232 (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
233 size = ((section & OMAP44XX_SYS_SIZE_MASK) >>
234 OMAP44XX_SYS_SIZE_SHIFT);
246 * Description: sets uboots idea of sdram size
251 gd->ram_size = omap4_sdram_size();
257 * Print board information
261 puts(sysinfo.board_string);
266 * This function is called by start_armboot. You can reliably use static
267 * data. Any boot-time function that require static data should be
270 int arch_cpu_init(void)
275 #ifndef CONFIG_SYS_L2CACHE_OFF
276 void v7_outer_cache_enable(void)
278 set_pl310_ctrl_reg(1);
281 void v7_outer_cache_disable(void)
283 set_pl310_ctrl_reg(0);