3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
42 * printing to console doesn't work unless
43 * this code is executed from SPL
45 #define printf(fmt, args...)
49 #define abs(x) (((x) < 0) ? ((x)*-1) : (x))
51 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
53 const u32 sys_clk_array[8] = {
54 12000000, /* 12 MHz */
55 13000000, /* 13 MHz */
56 16800000, /* 16.8 MHz */
57 19200000, /* 19.2 MHz */
58 26000000, /* 26 MHz */
59 27000000, /* 27 MHz */
60 38400000, /* 38.4 MHz */
64 * The M & N values in the following tables are created using the
66 * tools/omap/clocks_get_m_n.c
67 * Please use this tool for creating the table for any new frequency.
70 /* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
71 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
72 {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
73 {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
74 {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
75 {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
76 {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
77 {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
78 {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
81 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
82 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
83 {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
84 {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
85 {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
86 {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
87 {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
88 {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
89 {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
92 /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
93 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
94 {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
95 {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
96 {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
97 {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
98 {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
99 {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
100 {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
103 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
104 {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
105 {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
106 {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
107 {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
108 {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
109 {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
110 {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
113 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
114 {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
115 {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
116 {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
117 {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
118 {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
119 {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
120 {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
123 static const struct dpll_params
124 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
125 {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
126 {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
127 {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
128 {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
129 {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
130 {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
131 {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
134 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
135 {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
136 {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
137 {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
138 {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
139 {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
140 {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
141 {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
144 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
145 {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
146 {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
147 {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
148 {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
149 {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
150 {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
151 {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
154 /* ABE M & N values with sys_clk as source */
155 static const struct dpll_params
156 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
157 {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
158 {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
159 {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
160 {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
161 {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
162 {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
163 {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
166 /* ABE M & N values with 32K clock as source */
167 static const struct dpll_params abe_dpll_params_32k_196608khz = {
168 750, 0, 1, 1, -1, -1, -1, -1
171 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
172 {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
181 void setup_post_dividers(u32 *const base, const struct dpll_params *params)
183 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
185 /* Setup post-dividers */
187 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
189 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
191 writel(params->m4, &dpll_regs->cm_div_m4_dpll);
193 writel(params->m5, &dpll_regs->cm_div_m5_dpll);
195 writel(params->m6, &dpll_regs->cm_div_m6_dpll);
197 writel(params->m7, &dpll_regs->cm_div_m7_dpll);
203 * Resulting MPU frequencies:
204 * 4430 ES1.0 : 600 MHz
205 * 4430 ES2.x : 792 MHz (OPP Turbo)
206 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
208 const struct dpll_params *get_mpu_dpll_params(void)
210 u32 omap_rev, sysclk_ind;
212 omap_rev = omap_revision();
213 sysclk_ind = get_sys_clk_index();
215 if (omap_rev == OMAP4430_ES1_0)
216 return &mpu_dpll_params_1200mhz[sysclk_ind];
217 else if (omap_rev < OMAP4460_ES1_0)
218 return &mpu_dpll_params_1600mhz[sysclk_ind];
220 return &mpu_dpll_params_1400mhz[sysclk_ind];
223 const struct dpll_params *get_core_dpll_params(void)
225 u32 sysclk_ind = get_sys_clk_index();
227 switch (omap_revision()) {
229 return &core_dpll_params_es1_1524mhz[sysclk_ind];
231 case OMAP4430_SILICON_ID_INVALID:
233 return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
235 return &core_dpll_params_1600mhz[sysclk_ind];
240 const struct dpll_params *get_per_dpll_params(void)
242 u32 sysclk_ind = get_sys_clk_index();
243 return &per_dpll_params_1536mhz[sysclk_ind];
246 const struct dpll_params *get_iva_dpll_params(void)
248 u32 sysclk_ind = get_sys_clk_index();
249 return &iva_dpll_params_1862mhz[sysclk_ind];
252 const struct dpll_params *get_usb_dpll_params(void)
254 u32 sysclk_ind = get_sys_clk_index();
255 return &usb_dpll_params_1920mhz[sysclk_ind];
258 const struct dpll_params *get_abe_dpll_params(void)
260 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
261 u32 sysclk_ind = get_sys_clk_index();
262 return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
264 return &abe_dpll_params_32k_196608khz;
269 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
270 * We set the maximum voltages allowed here because Smart-Reflex is not
271 * enabled in bootloader. Voltage initialization in the kernel will set
272 * these to the nominal values after enabling Smart-Reflex
274 void scale_vcores(void)
278 omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
280 omap_rev = omap_revision();
283 * Scale Voltage rails:
288 if (omap_rev < OMAP4460_ES1_0) {
291 * VDD_CORE = TWL6030 VCORE3
292 * VDD_MPU = TWL6030 VCORE1
293 * VDD_IVA = TWL6030 VCORE2
296 do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
300 * Setting a high voltage for Nitro mode as smart reflex is not
301 * enabled. We use the maximum possible value in the AVS range
302 * because the next higher voltage in the discrete range
303 * (code >= 0b111010) is way too high.
306 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
308 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
313 * VDD_CORE = TWL6030 VCORE1
315 * VDD_IVA = TWL6030 VCORE2
318 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
321 do_scale_tps62361(TPS62361_VSEL0_GPIO,
322 TPS62361_REG_ADDR_SET1, volt);
323 /* VCORE 2 - supplies vdd_iva */
325 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
330 * Enable essential clock domains, modules and
331 * do some additional special settings needed
333 void enable_basic_clocks(void)
335 u32 *const clk_domains_essential[] = {
336 &prcm->cm_l4per_clkstctrl,
337 &prcm->cm_l3init_clkstctrl,
338 &prcm->cm_memif_clkstctrl,
339 &prcm->cm_l4cfg_clkstctrl,
343 u32 *const clk_modules_hw_auto_essential[] = {
344 &prcm->cm_memif_emif_1_clkctrl,
345 &prcm->cm_memif_emif_2_clkctrl,
346 &prcm->cm_l4cfg_l4_cfg_clkctrl,
347 &prcm->cm_wkup_gpio1_clkctrl,
348 &prcm->cm_l4per_gpio2_clkctrl,
349 &prcm->cm_l4per_gpio3_clkctrl,
350 &prcm->cm_l4per_gpio4_clkctrl,
351 &prcm->cm_l4per_gpio5_clkctrl,
352 &prcm->cm_l4per_gpio6_clkctrl,
353 &prcm->cm_l3init_usbphy_clkctrl,
354 &prcm->cm_clksel_usb_60mhz,
355 &prcm->cm_l3init_hsusbtll_clkctrl,
359 u32 *const clk_modules_explicit_en_essential[] = {
360 &prcm->cm_wkup_gptimer1_clkctrl,
361 &prcm->cm_l3init_hsmmc1_clkctrl,
362 &prcm->cm_l3init_hsmmc2_clkctrl,
363 &prcm->cm_l4per_gptimer2_clkctrl,
364 &prcm->cm_wkup_wdtimer2_clkctrl,
365 &prcm->cm_l4per_uart3_clkctrl,
366 &prcm->cm_l3init_fsusb_clkctrl,
367 &prcm->cm_l3init_hsusbhost_clkctrl,
371 /* Enable optional additional functional clock for GPIO4 */
372 setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
373 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
375 /* Enable 96 MHz clock for MMC1 & MMC2 */
376 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
377 HSMMC_CLKCTRL_CLKSEL_MASK);
378 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
379 HSMMC_CLKCTRL_CLKSEL_MASK);
381 /* Select 32KHz clock as the source of GPTIMER1 */
382 setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
383 GPTIMER1_CLKCTRL_CLKSEL_MASK);
385 /* Enable optional 48M functional clock for USB PHY */
386 setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
387 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
389 do_enable_clocks(clk_domains_essential,
390 clk_modules_hw_auto_essential,
391 clk_modules_explicit_en_essential,
395 void enable_basic_uboot_clocks(void)
397 u32 *const clk_domains_essential[] = {
401 u32 *const clk_modules_hw_auto_essential[] = {
402 &prcm->cm_l3init_hsusbotg_clkctrl,
403 &prcm->cm_l3init_usbphy_clkctrl,
407 u32 *const clk_modules_explicit_en_essential[] = {
408 &prcm->cm_l4per_mcspi1_clkctrl,
409 &prcm->cm_l4per_i2c1_clkctrl,
410 &prcm->cm_l4per_i2c2_clkctrl,
411 &prcm->cm_l4per_i2c3_clkctrl,
412 &prcm->cm_l4per_i2c4_clkctrl,
416 do_enable_clocks(clk_domains_essential,
417 clk_modules_hw_auto_essential,
418 clk_modules_explicit_en_essential,
423 * Enable non-essential clock domains, modules and
424 * do some additional special settings needed
426 void enable_non_essential_clocks(void)
428 u32 *const clk_domains_non_essential[] = {
429 &prcm->cm_mpu_m3_clkstctrl,
430 &prcm->cm_ivahd_clkstctrl,
431 &prcm->cm_dsp_clkstctrl,
432 &prcm->cm_dss_clkstctrl,
433 &prcm->cm_sgx_clkstctrl,
434 &prcm->cm1_abe_clkstctrl,
435 &prcm->cm_c2c_clkstctrl,
436 &prcm->cm_cam_clkstctrl,
437 &prcm->cm_dss_clkstctrl,
438 &prcm->cm_sdma_clkstctrl,
442 u32 *const clk_modules_hw_auto_non_essential[] = {
443 &prcm->cm_mpu_m3_mpu_m3_clkctrl,
444 &prcm->cm_ivahd_ivahd_clkctrl,
445 &prcm->cm_ivahd_sl2_clkctrl,
446 &prcm->cm_dsp_dsp_clkctrl,
447 &prcm->cm_l3_2_gpmc_clkctrl,
448 &prcm->cm_l3instr_l3_3_clkctrl,
449 &prcm->cm_l3instr_l3_instr_clkctrl,
450 &prcm->cm_l3instr_intrconn_wp1_clkctrl,
451 &prcm->cm_l3init_hsi_clkctrl,
452 &prcm->cm_l3init_hsusbtll_clkctrl,
456 u32 *const clk_modules_explicit_en_non_essential[] = {
457 &prcm->cm1_abe_aess_clkctrl,
458 &prcm->cm1_abe_pdm_clkctrl,
459 &prcm->cm1_abe_dmic_clkctrl,
460 &prcm->cm1_abe_mcasp_clkctrl,
461 &prcm->cm1_abe_mcbsp1_clkctrl,
462 &prcm->cm1_abe_mcbsp2_clkctrl,
463 &prcm->cm1_abe_mcbsp3_clkctrl,
464 &prcm->cm1_abe_slimbus_clkctrl,
465 &prcm->cm1_abe_timer5_clkctrl,
466 &prcm->cm1_abe_timer6_clkctrl,
467 &prcm->cm1_abe_timer7_clkctrl,
468 &prcm->cm1_abe_timer8_clkctrl,
469 &prcm->cm1_abe_wdt3_clkctrl,
470 &prcm->cm_l4per_gptimer9_clkctrl,
471 &prcm->cm_l4per_gptimer10_clkctrl,
472 &prcm->cm_l4per_gptimer11_clkctrl,
473 &prcm->cm_l4per_gptimer3_clkctrl,
474 &prcm->cm_l4per_gptimer4_clkctrl,
475 &prcm->cm_l4per_hdq1w_clkctrl,
476 &prcm->cm_l4per_mcbsp4_clkctrl,
477 &prcm->cm_l4per_mcspi2_clkctrl,
478 &prcm->cm_l4per_mcspi3_clkctrl,
479 &prcm->cm_l4per_mcspi4_clkctrl,
480 &prcm->cm_l4per_mmcsd3_clkctrl,
481 &prcm->cm_l4per_mmcsd4_clkctrl,
482 &prcm->cm_l4per_mmcsd5_clkctrl,
483 &prcm->cm_l4per_uart1_clkctrl,
484 &prcm->cm_l4per_uart2_clkctrl,
485 &prcm->cm_l4per_uart4_clkctrl,
486 &prcm->cm_wkup_keyboard_clkctrl,
487 &prcm->cm_wkup_wdtimer2_clkctrl,
488 &prcm->cm_cam_iss_clkctrl,
489 &prcm->cm_cam_fdif_clkctrl,
490 &prcm->cm_dss_dss_clkctrl,
491 &prcm->cm_sgx_sgx_clkctrl,
492 &prcm->cm_l3init_hsusbhost_clkctrl,
493 &prcm->cm_l3init_fsusb_clkctrl,
497 /* Enable optional functional clock for ISS */
498 setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
500 /* Enable all optional functional clocks of DSS */
501 setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
503 do_enable_clocks(clk_domains_non_essential,
504 clk_modules_hw_auto_non_essential,
505 clk_modules_explicit_en_non_essential,
508 /* Put camera module in no sleep mode */
509 clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
510 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
511 MODULE_CLKCTRL_MODULEMODE_SHIFT);