3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
34 #include <asm/arch/clocks.h>
35 #include <asm/arch/sys_proto.h>
36 #include <asm/utils.h>
37 #include <asm/omap_gpio.h>
39 #ifndef CONFIG_SPL_BUILD
41 * printing to console doesn't work unless
42 * this code is executed from SPL
44 #define printf(fmt, args...)
48 #define abs(x) (((x) < 0) ? ((x)*-1) : (x))
50 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
52 static const u32 sys_clk_array[8] = {
53 12000000, /* 12 MHz */
54 13000000, /* 13 MHz */
55 16800000, /* 16.8 MHz */
56 19200000, /* 19.2 MHz */
57 26000000, /* 26 MHz */
58 27000000, /* 27 MHz */
59 38400000, /* 38.4 MHz */
63 * The M & N values in the following tables are created using the
65 * tools/omap/clocks_get_m_n.c
66 * Please use this tool for creating the table for any new frequency.
69 /* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
70 static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
71 {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
72 {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
73 {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
74 {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
75 {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
76 {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
77 {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
80 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
81 static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
82 {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
83 {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
84 {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
85 {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
86 {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
87 {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
88 {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
91 /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
92 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
93 {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
94 {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
95 {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
96 {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
97 {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
98 {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
99 {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
102 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
103 {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
104 {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
105 {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
106 {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
107 {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
108 {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
109 {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
112 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
113 {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
114 {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
115 {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
116 {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
117 {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
118 {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
119 {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
122 static const struct dpll_params
123 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
124 {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
125 {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
126 {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
127 {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
128 {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
129 {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
130 {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
133 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
134 {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
135 {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
136 {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
137 {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
138 {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
139 {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
140 {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
143 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
144 {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
145 {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
146 {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
147 {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
148 {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
149 {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
150 {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
153 /* ABE M & N values with sys_clk as source */
154 static const struct dpll_params
155 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
156 {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
157 {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
158 {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
159 {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
160 {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
161 {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
162 {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
165 /* ABE M & N values with 32K clock as source */
166 static const struct dpll_params abe_dpll_params_32k_196608khz = {
167 750, 0, 1, 1, -1, -1, -1, -1
171 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
172 {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
181 static inline u32 __get_sys_clk_index(void)
185 * For ES1 the ROM code calibration of sys clock is not reliable
186 * due to hw issue. So, use hard-coded value. If this value is not
187 * correct for any board over-ride this function in board file
188 * From ES2.0 onwards you will get this information from
191 if (omap_revision() == OMAP4430_ES1_0)
192 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
194 /* SYS_CLKSEL - 1 to match the dpll param array indices */
195 ind = (readl(&prcm->cm_sys_clksel) &
196 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
201 u32 get_sys_clk_index(void)
202 __attribute__ ((weak, alias("__get_sys_clk_index")));
204 u32 get_sys_clk_freq(void)
206 u8 index = get_sys_clk_index();
207 return sys_clk_array[index];
210 static inline void do_bypass_dpll(u32 *const base)
212 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
214 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
215 CM_CLKMODE_DPLL_DPLL_EN_MASK,
216 DPLL_EN_FAST_RELOCK_BYPASS <<
217 CM_CLKMODE_DPLL_EN_SHIFT);
220 static inline void wait_for_bypass(u32 *const base)
222 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
224 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
226 printf("Bypassing DPLL failed %p\n", base);
230 static inline void do_lock_dpll(u32 *const base)
232 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
234 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
235 CM_CLKMODE_DPLL_DPLL_EN_MASK,
236 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
239 static inline void wait_for_lock(u32 *const base)
241 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
243 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
244 &dpll_regs->cm_idlest_dpll, LDELAY)) {
245 printf("DPLL locking failed for %p\n", base);
250 static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
254 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
259 temp = readl(&dpll_regs->cm_clksel_dpll);
261 temp &= ~CM_CLKSEL_DPLL_M_MASK;
262 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
264 temp &= ~CM_CLKSEL_DPLL_N_MASK;
265 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
267 writel(temp, &dpll_regs->cm_clksel_dpll);
273 /* Setup post-dividers */
275 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
277 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
279 writel(params->m4, &dpll_regs->cm_div_m4_dpll);
281 writel(params->m5, &dpll_regs->cm_div_m5_dpll);
283 writel(params->m6, &dpll_regs->cm_div_m6_dpll);
285 writel(params->m7, &dpll_regs->cm_div_m7_dpll);
287 /* Wait till the DPLL locks */
292 const struct dpll_params *get_core_dpll_params(void)
294 u32 sysclk_ind = get_sys_clk_index();
296 switch (omap_revision()) {
298 return &core_dpll_params_es1_1524mhz[sysclk_ind];
300 case OMAP4430_SILICON_ID_INVALID:
302 return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
304 return &core_dpll_params_1600mhz[sysclk_ind];
308 u32 omap4_ddr_clk(void)
310 u32 ddr_clk, sys_clk_khz;
311 const struct dpll_params *core_dpll_params;
313 sys_clk_khz = get_sys_clk_freq() / 1000;
315 core_dpll_params = get_core_dpll_params();
317 debug("sys_clk %d\n ", sys_clk_khz * 1000);
319 /* Find Core DPLL locked frequency first */
320 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
321 (core_dpll_params->n + 1);
323 * DDR frequency is PHY_ROOT_CLK/2
324 * PHY_ROOT_CLK = Fdpll/2/M2
326 ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
328 ddr_clk *= 1000; /* convert to Hz */
329 debug("ddr_clk %d\n ", ddr_clk);
337 * Resulting MPU frequencies:
338 * 4430 ES1.0 : 600 MHz
339 * 4430 ES2.x : 792 MHz (OPP Turbo)
340 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
342 void configure_mpu_dpll(void)
344 const struct dpll_params *params;
345 struct dpll_regs *mpu_dpll_regs;
346 u32 omap4_rev, sysclk_ind;
348 omap4_rev = omap_revision();
349 sysclk_ind = get_sys_clk_index();
351 if (omap4_rev == OMAP4430_ES1_0)
352 params = &mpu_dpll_params_1200mhz[sysclk_ind];
353 else if (omap4_rev < OMAP4460_ES1_0)
354 params = &mpu_dpll_params_1584mhz[sysclk_ind];
356 params = &mpu_dpll_params_1840mhz[sysclk_ind];
358 /* DCC and clock divider settings for 4460 */
359 if (omap4_rev >= OMAP4460_ES1_0) {
361 (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
362 bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
363 clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
364 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
365 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
366 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
367 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
368 CM_CLKSEL_DCC_EN_MASK);
371 do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
372 debug("MPU DPLL locked\n");
375 static void setup_dplls(void)
377 u32 sysclk_ind, temp;
378 const struct dpll_params *params;
379 debug("setup_dplls\n");
381 sysclk_ind = get_sys_clk_index();
384 params = get_core_dpll_params(); /* default - safest */
386 * Do not lock the core DPLL now. Just set it up.
387 * Core DPLL will be locked after setting up EMIF
388 * using the FREQ_UPDATE method(freq_update_core())
390 do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
391 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
392 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
393 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
394 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
395 writel(temp, &prcm->cm_clksel_core);
396 debug("Core DPLL configured\n");
399 do_setup_dpll(&prcm->cm_clkmode_dpll_per,
400 &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
401 debug("PER DPLL locked\n");
404 configure_mpu_dpll();
407 static void setup_non_essential_dplls(void)
409 u32 sys_clk_khz, abe_ref_clk;
410 u32 sysclk_ind, sd_div, num, den;
411 const struct dpll_params *params;
413 sysclk_ind = get_sys_clk_index();
414 sys_clk_khz = get_sys_clk_freq() / 1000;
417 clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
418 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
420 do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
421 &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
425 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
426 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
427 * - where CLKINP is sys_clk in MHz
428 * Use CLKINP in KHz and adjust the denominator accordingly so
429 * that we have enough accuracy and at the same time no overflow
431 params = &usb_dpll_params_1920mhz[sysclk_ind];
432 num = params->m * sys_clk_khz;
433 den = (params->n + 1) * 250 * 1000;
436 clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
437 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
438 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
440 /* Now setup the dpll with the regular function */
441 do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
443 #ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
444 params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
445 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
447 params = &abe_dpll_params_32k_196608khz;
448 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
450 * We need to enable some additional options to achieve
451 * 196.608MHz from 32768 Hz
453 setbits_le32(&prcm->cm_clkmode_dpll_abe,
454 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
455 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
456 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
457 CM_CLKMODE_DPLL_REGM4XEN_MASK);
458 /* Spend 4 REFCLK cycles at each stage */
459 clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
460 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
461 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
464 /* Select the right reference clk */
465 clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
466 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
467 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
469 do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
472 static void do_scale_tps62361(u32 reg, u32 volt_mv)
476 step = volt_mv - TPS62361_BASE_VOLT_MV;
480 * Select SET1 in TPS62361:
481 * VSEL1 is grounded on board. So the following selects
482 * VSEL1 = 0 and VSEL0 = 1
484 omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0);
485 omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1);
487 temp = TPS62361_I2C_SLAVE_ADDR |
488 (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
489 (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
490 PRM_VC_VAL_BYPASS_VALID_BIT;
491 debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
493 writel(temp, &prcm->prm_vc_val_bypass);
494 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
495 &prcm->prm_vc_val_bypass, LDELAY)) {
496 puts("Scaling voltage failed for vdd_mpu from TPS\n");
500 static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
502 u32 temp, offset_code;
503 u32 step = 12660; /* 12.66 mV represented in uV */
504 u32 offset = volt_mv;
506 /* convert to uV for better accuracy in the calculations */
509 if (omap_revision() == OMAP4430_ES1_0)
510 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
512 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
514 offset_code = (offset + step - 1) / step;
515 /* The code starts at 1 not 0 */
518 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
521 temp = SMPS_I2C_SLAVE_ADDR |
522 (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
523 (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
524 PRM_VC_VAL_BYPASS_VALID_BIT;
525 writel(temp, &prcm->prm_vc_val_bypass);
526 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
527 &prcm->prm_vc_val_bypass, LDELAY)) {
528 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
533 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
534 * We set the maximum voltages allowed here because Smart-Reflex is not
535 * enabled in bootloader. Voltage initialization in the kernel will set
536 * these to the nominal values after enabling Smart-Reflex
538 static void scale_vcores(void)
540 u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
542 sys_clk_khz = get_sys_clk_freq() / 1000;
545 * Setup the dedicated I2C controller for Voltage Control
546 * I2C clk - high period 40% low period 60%
548 cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
549 cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
550 /* values to be set in register - less by 5 & 7 respectively */
553 temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
554 (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
555 writel(temp, &prcm->prm_vc_cfg_i2c_clk);
557 /* Disable high speed mode and all advanced features */
558 writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
560 omap4_rev = omap_revision();
561 /* TPS - supplies vdd_mpu on 4460 */
562 if (omap4_rev >= OMAP4460_ES1_0) {
564 do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
570 * 4430 : supplies vdd_mpu
571 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
572 * We use the maximum possible value in the AVS range because the next
573 * higher voltage in the discrete range (code >= 0b111010) is way too
576 * 4460 : supplies vdd_core
578 if (omap4_rev < OMAP4460_ES1_0) {
580 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
583 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
586 /* VCORE 2 - supplies vdd_iva */
588 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
592 * 4430 : supplies vdd_core
593 * 4460 : not connected
595 if (omap4_rev < OMAP4460_ES1_0) {
597 do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
601 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
603 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
604 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
605 debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
608 static inline void wait_for_clk_enable(u32 *clkctrl_addr)
610 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
613 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
614 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
616 clkctrl = readl(clkctrl_addr);
617 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
618 MODULE_CLKCTRL_IDLEST_SHIFT;
620 printf("Clock enable failed for 0x%p idlest 0x%x\n",
621 clkctrl_addr, clkctrl);
627 static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
630 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
631 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
632 debug("Enable clock module - 0x%08x\n", clkctrl_addr);
634 wait_for_clk_enable(clkctrl_addr);
638 * Enable essential clock domains, modules and
639 * do some additional special settings needed
641 static void enable_basic_clocks(void)
643 u32 i, max = 100, wait_for_enable = 1;
644 u32 *const clk_domains_essential[] = {
645 &prcm->cm_l4per_clkstctrl,
646 &prcm->cm_l3init_clkstctrl,
647 &prcm->cm_memif_clkstctrl,
648 &prcm->cm_l4cfg_clkstctrl,
652 u32 *const clk_modules_hw_auto_essential[] = {
653 &prcm->cm_wkup_gpio1_clkctrl,
654 &prcm->cm_l4per_gpio2_clkctrl,
655 &prcm->cm_l4per_gpio3_clkctrl,
656 &prcm->cm_l4per_gpio4_clkctrl,
657 &prcm->cm_l4per_gpio5_clkctrl,
658 &prcm->cm_l4per_gpio6_clkctrl,
659 &prcm->cm_memif_emif_1_clkctrl,
660 &prcm->cm_memif_emif_2_clkctrl,
661 &prcm->cm_l3init_hsusbotg_clkctrl,
662 &prcm->cm_l3init_usbphy_clkctrl,
663 &prcm->cm_l4cfg_l4_cfg_clkctrl,
667 u32 *const clk_modules_explicit_en_essential[] = {
668 &prcm->cm_l4per_gptimer2_clkctrl,
669 &prcm->cm_l3init_hsmmc1_clkctrl,
670 &prcm->cm_l3init_hsmmc2_clkctrl,
671 &prcm->cm_l4per_mcspi1_clkctrl,
672 &prcm->cm_wkup_gptimer1_clkctrl,
673 &prcm->cm_l4per_i2c1_clkctrl,
674 &prcm->cm_l4per_i2c2_clkctrl,
675 &prcm->cm_l4per_i2c3_clkctrl,
676 &prcm->cm_l4per_i2c4_clkctrl,
677 &prcm->cm_wkup_wdtimer2_clkctrl,
678 &prcm->cm_l4per_uart3_clkctrl,
682 /* Enable optional additional functional clock for GPIO4 */
683 setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
684 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
686 /* Enable 96 MHz clock for MMC1 & MMC2 */
687 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
688 HSMMC_CLKCTRL_CLKSEL_MASK);
689 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
690 HSMMC_CLKCTRL_CLKSEL_MASK);
692 /* Select 32KHz clock as the source of GPTIMER1 */
693 setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
694 GPTIMER1_CLKCTRL_CLKSEL_MASK);
696 /* Enable optional 48M functional clock for USB PHY */
697 setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
698 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
700 /* Put the clock domains in SW_WKUP mode */
701 for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
702 enable_clock_domain(clk_domains_essential[i],
703 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
706 /* Clock modules that need to be put in HW_AUTO */
707 for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
708 enable_clock_module(clk_modules_hw_auto_essential[i],
709 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
713 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
714 for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
715 enable_clock_module(clk_modules_explicit_en_essential[i],
716 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
720 /* Put the clock domains in HW_AUTO mode now */
721 for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
722 enable_clock_domain(clk_domains_essential[i],
723 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
728 * Enable non-essential clock domains, modules and
729 * do some additional special settings needed
731 static void enable_non_essential_clocks(void)
733 u32 i, max = 100, wait_for_enable = 0;
734 u32 *const clk_domains_non_essential[] = {
735 &prcm->cm_mpu_m3_clkstctrl,
736 &prcm->cm_ivahd_clkstctrl,
737 &prcm->cm_dsp_clkstctrl,
738 &prcm->cm_dss_clkstctrl,
739 &prcm->cm_sgx_clkstctrl,
740 &prcm->cm1_abe_clkstctrl,
741 &prcm->cm_c2c_clkstctrl,
742 &prcm->cm_cam_clkstctrl,
743 &prcm->cm_dss_clkstctrl,
744 &prcm->cm_sdma_clkstctrl,
748 u32 *const clk_modules_hw_auto_non_essential[] = {
749 &prcm->cm_mpu_m3_mpu_m3_clkctrl,
750 &prcm->cm_ivahd_ivahd_clkctrl,
751 &prcm->cm_ivahd_sl2_clkctrl,
752 &prcm->cm_dsp_dsp_clkctrl,
753 &prcm->cm_l3_2_gpmc_clkctrl,
754 &prcm->cm_l3instr_l3_3_clkctrl,
755 &prcm->cm_l3instr_l3_instr_clkctrl,
756 &prcm->cm_l3instr_intrconn_wp1_clkctrl,
757 &prcm->cm_l3init_hsi_clkctrl,
758 &prcm->cm_l3init_hsusbtll_clkctrl,
762 u32 *const clk_modules_explicit_en_non_essential[] = {
763 &prcm->cm1_abe_aess_clkctrl,
764 &prcm->cm1_abe_pdm_clkctrl,
765 &prcm->cm1_abe_dmic_clkctrl,
766 &prcm->cm1_abe_mcasp_clkctrl,
767 &prcm->cm1_abe_mcbsp1_clkctrl,
768 &prcm->cm1_abe_mcbsp2_clkctrl,
769 &prcm->cm1_abe_mcbsp3_clkctrl,
770 &prcm->cm1_abe_slimbus_clkctrl,
771 &prcm->cm1_abe_timer5_clkctrl,
772 &prcm->cm1_abe_timer6_clkctrl,
773 &prcm->cm1_abe_timer7_clkctrl,
774 &prcm->cm1_abe_timer8_clkctrl,
775 &prcm->cm1_abe_wdt3_clkctrl,
776 &prcm->cm_l4per_gptimer9_clkctrl,
777 &prcm->cm_l4per_gptimer10_clkctrl,
778 &prcm->cm_l4per_gptimer11_clkctrl,
779 &prcm->cm_l4per_gptimer3_clkctrl,
780 &prcm->cm_l4per_gptimer4_clkctrl,
781 &prcm->cm_l4per_hdq1w_clkctrl,
782 &prcm->cm_l4per_mcbsp4_clkctrl,
783 &prcm->cm_l4per_mcspi2_clkctrl,
784 &prcm->cm_l4per_mcspi3_clkctrl,
785 &prcm->cm_l4per_mcspi4_clkctrl,
786 &prcm->cm_l4per_mmcsd3_clkctrl,
787 &prcm->cm_l4per_mmcsd4_clkctrl,
788 &prcm->cm_l4per_mmcsd5_clkctrl,
789 &prcm->cm_l4per_uart1_clkctrl,
790 &prcm->cm_l4per_uart2_clkctrl,
791 &prcm->cm_l4per_uart4_clkctrl,
792 &prcm->cm_wkup_keyboard_clkctrl,
793 &prcm->cm_wkup_wdtimer2_clkctrl,
794 &prcm->cm_cam_iss_clkctrl,
795 &prcm->cm_cam_fdif_clkctrl,
796 &prcm->cm_dss_dss_clkctrl,
797 &prcm->cm_sgx_sgx_clkctrl,
798 &prcm->cm_l3init_hsusbhost_clkctrl,
799 &prcm->cm_l3init_fsusb_clkctrl,
803 /* Enable optional functional clock for ISS */
804 setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
806 /* Enable all optional functional clocks of DSS */
807 setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
810 /* Put the clock domains in SW_WKUP mode */
811 for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
812 enable_clock_domain(clk_domains_non_essential[i],
813 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
816 /* Clock modules that need to be put in HW_AUTO */
817 for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
818 enable_clock_module(clk_modules_hw_auto_non_essential[i],
819 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
823 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
824 for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
826 enable_clock_module(clk_modules_explicit_en_non_essential[i],
827 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
831 /* Put the clock domains in HW_AUTO mode now */
832 for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
833 enable_clock_domain(clk_domains_non_essential[i],
834 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
837 /* Put camera module in no sleep mode */
838 clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
839 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
840 MODULE_CLKCTRL_MODULEMODE_SHIFT);
844 void freq_update_core(void)
846 u32 freq_config1 = 0;
847 const struct dpll_params *core_dpll_params;
849 core_dpll_params = get_core_dpll_params();
850 /* Put EMIF clock domain in sw wakeup mode */
851 enable_clock_domain(&prcm->cm_memif_clkstctrl,
852 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
853 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
854 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
856 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
857 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
859 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
860 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
862 freq_config1 |= (core_dpll_params->m2 <<
863 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
864 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
866 writel(freq_config1, &prcm->cm_shadow_freq_config1);
867 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
868 &prcm->cm_shadow_freq_config1, LDELAY)) {
869 puts("FREQ UPDATE procedure failed!!");
873 /* Put EMIF clock domain back in hw auto mode */
874 enable_clock_domain(&prcm->cm_memif_clkstctrl,
875 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
876 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
877 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
880 void bypass_dpll(u32 *const base)
882 do_bypass_dpll(base);
883 wait_for_bypass(base);
886 void lock_dpll(u32 *const base)
892 void setup_clocks_for_console(void)
894 /* Do not add any spl_debug prints in this function */
895 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
896 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
897 CD_CLKCTRL_CLKTRCTRL_SHIFT);
899 /* Enable all UARTs - console will be on one of them */
900 clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
901 MODULE_CLKCTRL_MODULEMODE_MASK,
902 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
903 MODULE_CLKCTRL_MODULEMODE_SHIFT);
905 clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
906 MODULE_CLKCTRL_MODULEMODE_MASK,
907 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
908 MODULE_CLKCTRL_MODULEMODE_SHIFT);
910 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
911 MODULE_CLKCTRL_MODULEMODE_MASK,
912 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
913 MODULE_CLKCTRL_MODULEMODE_SHIFT);
915 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
916 MODULE_CLKCTRL_MODULEMODE_MASK,
917 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
918 MODULE_CLKCTRL_MODULEMODE_SHIFT);
920 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
921 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
922 CD_CLKCTRL_CLKTRCTRL_SHIFT);
927 switch (omap4_hw_init_context()) {
928 case OMAP_INIT_CONTEXT_SPL:
929 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
930 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
931 enable_basic_clocks();
934 setup_non_essential_dplls();
935 enable_non_essential_clocks();