3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
42 * printing to console doesn't work unless
43 * this code is executed from SPL
45 #define printf(fmt, args...)
49 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
51 const u32 sys_clk_array[8] = {
52 12000000, /* 12 MHz */
53 13000000, /* 13 MHz */
54 16800000, /* 16.8 MHz */
55 19200000, /* 19.2 MHz */
56 26000000, /* 26 MHz */
57 27000000, /* 27 MHz */
58 38400000, /* 38.4 MHz */
62 * The M & N values in the following tables are created using the
64 * tools/omap/clocks_get_m_n.c
65 * Please use this tool for creating the table for any new frequency.
68 /* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
69 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
70 {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
71 {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
72 {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
73 {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
74 {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
75 {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
76 {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
79 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
80 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
81 {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
82 {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
83 {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
84 {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
85 {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
86 {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
87 {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
90 /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
91 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
92 {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
93 {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
94 {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
95 {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
96 {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
97 {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
98 {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
101 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
102 {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
103 {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
104 {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
105 {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
106 {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
107 {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
108 {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
111 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
112 {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
113 {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
114 {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
115 {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
116 {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
117 {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
118 {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
121 static const struct dpll_params
122 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
123 {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
124 {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
125 {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
126 {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
127 {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
128 {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
129 {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
132 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
133 {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
134 {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
135 {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
136 {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
137 {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
138 {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
139 {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
142 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
143 {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
144 {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
145 {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
146 {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
147 {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
148 {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
149 {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
152 /* ABE M & N values with sys_clk as source */
153 static const struct dpll_params
154 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
155 {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
156 {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
157 {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
158 {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
159 {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
160 {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
161 {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
164 /* ABE M & N values with 32K clock as source */
165 static const struct dpll_params abe_dpll_params_32k_196608khz = {
166 750, 0, 1, 1, -1, -1, -1, -1
169 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
170 {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
171 {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
172 {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
173 {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
174 {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
175 {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
176 {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
179 void setup_post_dividers(u32 *const base, const struct dpll_params *params)
181 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
183 /* Setup post-dividers */
185 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
187 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
189 writel(params->m4, &dpll_regs->cm_div_m4_dpll);
191 writel(params->m5, &dpll_regs->cm_div_m5_dpll);
193 writel(params->m6, &dpll_regs->cm_div_m6_dpll);
195 writel(params->m7, &dpll_regs->cm_div_m7_dpll);
201 * Resulting MPU frequencies:
202 * 4430 ES1.0 : 600 MHz
203 * 4430 ES2.x : 792 MHz (OPP Turbo)
204 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
206 const struct dpll_params *get_mpu_dpll_params(void)
208 u32 omap_rev, sysclk_ind;
210 omap_rev = omap_revision();
211 sysclk_ind = get_sys_clk_index();
213 if (omap_rev == OMAP4430_ES1_0)
214 return &mpu_dpll_params_1200mhz[sysclk_ind];
215 else if (omap_rev < OMAP4460_ES1_0)
216 return &mpu_dpll_params_1600mhz[sysclk_ind];
218 return &mpu_dpll_params_1400mhz[sysclk_ind];
221 const struct dpll_params *get_core_dpll_params(void)
223 u32 sysclk_ind = get_sys_clk_index();
225 switch (omap_revision()) {
227 return &core_dpll_params_es1_1524mhz[sysclk_ind];
229 case OMAP4430_SILICON_ID_INVALID:
231 return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
233 return &core_dpll_params_1600mhz[sysclk_ind];
238 const struct dpll_params *get_per_dpll_params(void)
240 u32 sysclk_ind = get_sys_clk_index();
241 return &per_dpll_params_1536mhz[sysclk_ind];
244 const struct dpll_params *get_iva_dpll_params(void)
246 u32 sysclk_ind = get_sys_clk_index();
247 return &iva_dpll_params_1862mhz[sysclk_ind];
250 const struct dpll_params *get_usb_dpll_params(void)
252 u32 sysclk_ind = get_sys_clk_index();
253 return &usb_dpll_params_1920mhz[sysclk_ind];
256 const struct dpll_params *get_abe_dpll_params(void)
258 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
259 u32 sysclk_ind = get_sys_clk_index();
260 return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
262 return &abe_dpll_params_32k_196608khz;
267 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
268 * We set the maximum voltages allowed here because Smart-Reflex is not
269 * enabled in bootloader. Voltage initialization in the kernel will set
270 * these to the nominal values after enabling Smart-Reflex
272 void scale_vcores(void)
276 omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
278 omap_rev = omap_revision();
281 * Scale Voltage rails:
286 if (omap_rev < OMAP4460_ES1_0) {
289 * VDD_CORE = TWL6030 VCORE3
290 * VDD_MPU = TWL6030 VCORE1
291 * VDD_IVA = TWL6030 VCORE2
294 do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
298 * Setting a high voltage for Nitro mode as smart reflex is not
299 * enabled. We use the maximum possible value in the AVS range
300 * because the next higher voltage in the discrete range
301 * (code >= 0b111010) is way too high.
304 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
306 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
311 * VDD_CORE = TWL6030 VCORE1
313 * VDD_IVA = TWL6030 VCORE2
316 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
319 do_scale_tps62361(TPS62361_VSEL0_GPIO,
320 TPS62361_REG_ADDR_SET1, volt);
321 /* VCORE 2 - supplies vdd_iva */
323 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
327 u32 get_offset_code(u32 offset)
329 u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
331 if (omap_revision() == OMAP4430_ES1_0)
332 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
334 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
336 offset_code = (offset + step - 1) / step;
338 /* The code starts at 1 not 0 */
339 return ++offset_code;
343 * Enable essential clock domains, modules and
344 * do some additional special settings needed
346 void enable_basic_clocks(void)
348 u32 *const clk_domains_essential[] = {
349 &prcm->cm_l4per_clkstctrl,
350 &prcm->cm_l3init_clkstctrl,
351 &prcm->cm_memif_clkstctrl,
352 &prcm->cm_l4cfg_clkstctrl,
356 u32 *const clk_modules_hw_auto_essential[] = {
357 &prcm->cm_memif_emif_1_clkctrl,
358 &prcm->cm_memif_emif_2_clkctrl,
359 &prcm->cm_l4cfg_l4_cfg_clkctrl,
360 &prcm->cm_wkup_gpio1_clkctrl,
361 &prcm->cm_l4per_gpio2_clkctrl,
362 &prcm->cm_l4per_gpio3_clkctrl,
363 &prcm->cm_l4per_gpio4_clkctrl,
364 &prcm->cm_l4per_gpio5_clkctrl,
365 &prcm->cm_l4per_gpio6_clkctrl,
366 &prcm->cm_l3init_usbphy_clkctrl,
367 &prcm->cm_clksel_usb_60mhz,
368 &prcm->cm_l3init_hsusbtll_clkctrl,
372 u32 *const clk_modules_explicit_en_essential[] = {
373 &prcm->cm_wkup_gptimer1_clkctrl,
374 &prcm->cm_l3init_hsmmc1_clkctrl,
375 &prcm->cm_l3init_hsmmc2_clkctrl,
376 &prcm->cm_l4per_gptimer2_clkctrl,
377 &prcm->cm_wkup_wdtimer2_clkctrl,
378 &prcm->cm_l4per_uart3_clkctrl,
379 &prcm->cm_l3init_hsusbhost_clkctrl,
383 /* Enable optional additional functional clock for GPIO4 */
384 setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
385 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
387 /* Enable 96 MHz clock for MMC1 & MMC2 */
388 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
389 HSMMC_CLKCTRL_CLKSEL_MASK);
390 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
391 HSMMC_CLKCTRL_CLKSEL_MASK);
393 /* Select 32KHz clock as the source of GPTIMER1 */
394 setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
395 GPTIMER1_CLKCTRL_CLKSEL_MASK);
397 /* Enable optional 48M functional clock for USB PHY */
398 setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
399 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
401 do_enable_clocks(clk_domains_essential,
402 clk_modules_hw_auto_essential,
403 clk_modules_explicit_en_essential,
407 void enable_basic_uboot_clocks(void)
409 u32 *const clk_domains_essential[] = {
413 u32 *const clk_modules_hw_auto_essential[] = {
414 &prcm->cm_l3init_hsusbotg_clkctrl,
415 &prcm->cm_l3init_usbphy_clkctrl,
419 u32 *const clk_modules_explicit_en_essential[] = {
420 &prcm->cm_l4per_mcspi1_clkctrl,
421 &prcm->cm_l4per_i2c1_clkctrl,
422 &prcm->cm_l4per_i2c2_clkctrl,
423 &prcm->cm_l4per_i2c3_clkctrl,
424 &prcm->cm_l4per_i2c4_clkctrl,
428 do_enable_clocks(clk_domains_essential,
429 clk_modules_hw_auto_essential,
430 clk_modules_explicit_en_essential,
435 * Enable non-essential clock domains, modules and
436 * do some additional special settings needed
438 void enable_non_essential_clocks(void)
440 u32 *const clk_domains_non_essential[] = {
441 &prcm->cm_mpu_m3_clkstctrl,
442 &prcm->cm_ivahd_clkstctrl,
443 &prcm->cm_dsp_clkstctrl,
444 &prcm->cm_dss_clkstctrl,
445 &prcm->cm_sgx_clkstctrl,
446 &prcm->cm1_abe_clkstctrl,
447 &prcm->cm_c2c_clkstctrl,
448 &prcm->cm_cam_clkstctrl,
449 &prcm->cm_dss_clkstctrl,
450 &prcm->cm_sdma_clkstctrl,
454 u32 *const clk_modules_hw_auto_non_essential[] = {
455 &prcm->cm_l3_2_gpmc_clkctrl,
456 &prcm->cm_l3instr_l3_3_clkctrl,
457 &prcm->cm_l3instr_l3_instr_clkctrl,
458 &prcm->cm_l3instr_intrconn_wp1_clkctrl,
459 &prcm->cm_l3init_hsi_clkctrl,
460 &prcm->cm_l3init_hsusbtll_clkctrl,
464 u32 *const clk_modules_explicit_en_non_essential[] = {
465 &prcm->cm1_abe_aess_clkctrl,
466 &prcm->cm1_abe_pdm_clkctrl,
467 &prcm->cm1_abe_dmic_clkctrl,
468 &prcm->cm1_abe_mcasp_clkctrl,
469 &prcm->cm1_abe_mcbsp1_clkctrl,
470 &prcm->cm1_abe_mcbsp2_clkctrl,
471 &prcm->cm1_abe_mcbsp3_clkctrl,
472 &prcm->cm1_abe_slimbus_clkctrl,
473 &prcm->cm1_abe_timer5_clkctrl,
474 &prcm->cm1_abe_timer6_clkctrl,
475 &prcm->cm1_abe_timer7_clkctrl,
476 &prcm->cm1_abe_timer8_clkctrl,
477 &prcm->cm1_abe_wdt3_clkctrl,
478 &prcm->cm_l4per_gptimer9_clkctrl,
479 &prcm->cm_l4per_gptimer10_clkctrl,
480 &prcm->cm_l4per_gptimer11_clkctrl,
481 &prcm->cm_l4per_gptimer3_clkctrl,
482 &prcm->cm_l4per_gptimer4_clkctrl,
483 &prcm->cm_l4per_hdq1w_clkctrl,
484 &prcm->cm_l4per_mcbsp4_clkctrl,
485 &prcm->cm_l4per_mcspi2_clkctrl,
486 &prcm->cm_l4per_mcspi3_clkctrl,
487 &prcm->cm_l4per_mcspi4_clkctrl,
488 &prcm->cm_l4per_mmcsd3_clkctrl,
489 &prcm->cm_l4per_mmcsd4_clkctrl,
490 &prcm->cm_l4per_mmcsd5_clkctrl,
491 &prcm->cm_l4per_uart1_clkctrl,
492 &prcm->cm_l4per_uart2_clkctrl,
493 &prcm->cm_l4per_uart4_clkctrl,
494 &prcm->cm_wkup_keyboard_clkctrl,
495 &prcm->cm_wkup_wdtimer2_clkctrl,
496 &prcm->cm_cam_iss_clkctrl,
497 &prcm->cm_cam_fdif_clkctrl,
498 &prcm->cm_dss_dss_clkctrl,
499 &prcm->cm_sgx_sgx_clkctrl,
500 &prcm->cm_l3init_hsusbhost_clkctrl,
504 /* Enable optional functional clock for ISS */
505 setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
507 /* Enable all optional functional clocks of DSS */
508 setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
510 do_enable_clocks(clk_domains_non_essential,
511 clk_modules_hw_auto_non_essential,
512 clk_modules_explicit_en_non_essential,
515 /* Put camera module in no sleep mode */
516 clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
517 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
518 MODULE_CLKCTRL_MODULEMODE_SHIFT);