5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/emif.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
35 static inline u32 emif_num(u32 base)
37 if (base == OMAP44XX_EMIF1)
39 else if (base == OMAP44XX_EMIF2)
45 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
48 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
50 mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
51 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
52 if (omap_revision() == OMAP4430_ES2_0)
53 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
55 mr = readl(&emif->emif_lpddr2_mode_reg_data);
56 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
61 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
63 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
65 mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
66 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
67 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
70 void emif_reset_phy(u32 base)
72 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
75 iodft = readl(&emif->emif_iodft_tlgc);
76 iodft |= OMAP44XX_REG_RESET_PHY_MASK;
77 writel(iodft, &emif->emif_iodft_tlgc);
80 static void do_lpddr2_init(u32 base, u32 cs)
84 /* Wait till device auto initialization is complete */
85 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
87 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
90 * Enough loops assuming a maximum of 2GHz
93 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
94 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
96 * Enable refresh along with writing MR2
97 * Encoding of RL in MR2 is (RL - 2)
99 mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
100 set_mr(base, cs, mr_addr, RL_FINAL - 2);
103 static void lpddr2_init(u32 base, const struct emif_regs *regs)
105 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
108 clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
111 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
112 * when EMIF_SDRAM_CONFIG register is written
114 setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
117 * Set the SDRAM_CONFIG and PHY_CTRL for the
118 * un-locked frequency & default RL
120 writel(regs->sdram_config_init, &emif->emif_sdram_config);
121 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
123 do_lpddr2_init(base, CS0);
124 if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
125 do_lpddr2_init(base, CS1);
127 writel(regs->sdram_config, &emif->emif_sdram_config);
128 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
130 /* Enable refresh now */
131 clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
135 static void emif_update_timings(u32 base, const struct emif_regs *regs)
137 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
139 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
140 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
141 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
142 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
143 if (omap_revision() == OMAP4430_ES1_0) {
144 /* ES1 bug EMIF should be in force idle during freq_update */
145 writel(0, &emif->emif_pwr_mgmt_ctrl);
147 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
148 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
150 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
151 writel(regs->zq_config, &emif->emif_zq_config);
152 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
153 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
156 * In a specific situation, the OCP interface between the DMM and
158 * 1. A TILER port is used to perform 2D burst writes of
159 * width 1 and height 8
160 * 2. ELLAn port is used to perform reads
161 * 3. All accesses are routed to the same EMIF controller
163 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
164 * be kept higher than default 0x7. As per recommondation 0x0A will
165 * be used for better performance with REG_LL_THRESH_MAX = 0x00
167 if (omap_revision() == OMAP4430_ES1_0) {
168 writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
169 &emif->emif_l3_config);
173 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
174 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
176 static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
177 static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
178 static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
181 * Organization and refresh requirements for LPDDR2 devices of different
182 * types and densities. Derived from JESD209-2 section 2.4
184 const struct lpddr2_addressing addressing_table[] = {
185 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
186 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
187 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
188 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
189 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
190 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
191 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
192 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
193 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
194 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
195 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
198 static const u32 lpddr2_density_2_size_in_mbytes[] = {
212 * Calculate the period of DDR clock from frequency value and set the
213 * denominator and numerator in global variables for easy access later
215 static void set_ddr_clk_period(u32 freq)
219 * period_in_ns = 10^9/freq
223 cancel_out(T_num, T_den, 200);
228 * Convert time in nano seconds to number of cycles of DDR clock
230 static inline u32 ns_2_cycles(u32 ns)
232 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
236 * ns_2_cycles with the difference that the time passed is 2 times the actual
237 * value(to avoid fractions). The cycles returned is for the original value of
238 * the timing parameter
240 static inline u32 ns_x2_2_cycles(u32 ns)
242 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
246 * Find addressing table index based on the device's type(S2 or S4) and
249 s8 addressing_table_index(u8 type, u8 density, u8 width)
252 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
256 * Look at the way ADDR_TABLE_INDEX* values have been defined
257 * in emif.h compared to LPDDR2_DENSITY_* values
258 * The table is layed out in the increasing order of density
259 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
262 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
263 index = ADDR_TABLE_INDEX1GS2;
264 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
265 index = ADDR_TABLE_INDEX2GS2;
269 debug("emif: addressing table index %d\n", index);
275 * Find the the right timing table from the array of timing
276 * tables of the device using DDR clock frequency
278 static const struct lpddr2_ac_timings *get_timings_table(const struct
279 lpddr2_ac_timings const *const *device_timings,
282 u32 i, temp, freq_nearest;
283 const struct lpddr2_ac_timings *timings = 0;
285 emif_assert(freq <= MAX_LPDDR2_FREQ);
286 emif_assert(device_timings);
289 * Start with the maximum allowed frequency - that is always safe
291 freq_nearest = MAX_LPDDR2_FREQ;
293 * Find the timings table that has the max frequency value:
294 * i. Above or equal to the DDR frequency - safe
295 * ii. The lowest that satisfies condition (i) - optimal
297 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
298 temp = device_timings[i]->max_freq;
299 if ((temp >= freq) && (temp <= freq_nearest)) {
301 timings = device_timings[i];
304 debug("emif: timings table: %d\n", freq_nearest);
309 * Finds the value of emif_sdram_config_reg
310 * All parameters are programmed based on the device on CS0.
311 * If there is a device on CS1, it will be same as that on CS0 or
312 * it will be NVM. We don't support NVM yet.
313 * If cs1_device pointer is NULL it is assumed that there is no device
316 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
317 const struct lpddr2_device_details *cs1_device,
318 const struct lpddr2_addressing *addressing,
323 config_reg |= (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
324 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
325 OMAP44XX_REG_IBANK_POS_SHIFT;
327 config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
329 config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
331 config_reg |= addressing->row_sz[cs0_device->io_width] <<
332 OMAP44XX_REG_ROWSIZE_SHIFT;
334 config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
336 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
337 OMAP44XX_REG_EBANK_SHIFT;
339 config_reg |= addressing->col_sz[cs0_device->io_width] <<
340 OMAP44XX_REG_PAGESIZE_SHIFT;
345 static u32 get_sdram_ref_ctrl(u32 freq,
346 const struct lpddr2_addressing *addressing)
348 u32 ref_ctrl = 0, val = 0, freq_khz;
349 freq_khz = freq / 1000;
351 * refresh rate to be set is 'tREFI * freq in MHz
352 * division by 10000 to account for khz and x10 in t_REFI_us_x10
354 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
355 ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
360 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
361 const struct lpddr2_min_tck *min_tck,
362 const struct lpddr2_addressing *addressing)
364 u32 tim1 = 0, val = 0;
365 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
366 tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
368 if (addressing->num_banks == BANKS8)
369 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
372 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
374 tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
376 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
377 tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
379 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
380 tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
382 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
383 tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
385 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
386 tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
388 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
389 tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
394 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
395 const struct lpddr2_min_tck *min_tck)
397 u32 tim2 = 0, val = 0;
398 val = max(min_tck->tCKE, timings->tCKE) - 1;
399 tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
401 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
402 tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
405 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
408 val = ns_2_cycles(timings->tXSR) - 1;
409 tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
410 tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
412 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
413 tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
418 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
419 const struct lpddr2_min_tck *min_tck,
420 const struct lpddr2_addressing *addressing)
422 u32 tim3 = 0, val = 0;
423 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
424 tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
426 val = ns_2_cycles(timings->tRFCab) - 1;
427 tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
429 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
430 tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
432 val = ns_2_cycles(timings->tZQCS) - 1;
433 tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
435 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
436 tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
441 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
442 const struct lpddr2_addressing *addressing,
448 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
449 addressing->t_REFI_us_x10;
452 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
453 addressing->t_REFI_us_x10;
454 zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
456 zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
458 zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
460 zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
463 * Assuming that two chipselects have a single calibration resistor
464 * If there are indeed two calibration resistors, then this flag should
465 * be enabled to take advantage of dual calibration feature.
466 * This data should ideally come from board files. But considering
467 * that none of the boards today have calibration resistors per CS,
468 * it would be an unnecessary overhead.
470 zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
472 zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
474 zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
479 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
480 const struct lpddr2_addressing *addressing,
483 u32 alert = 0, interval;
485 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
488 alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
490 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
492 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
494 alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
496 alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
498 alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
503 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
505 u32 idle = 0, val = 0;
507 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
509 /*Maximum value in normal conditions - suggested by hw team */
511 idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
513 idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
518 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
520 u32 phy = 0, val = 0;
522 phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
524 if (freq <= 100000000)
525 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
526 else if (freq <= 200000000)
527 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
529 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
530 phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
532 /* Other fields are constant magic values. Hardcode them together */
533 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
534 OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
539 static u32 get_emif_mem_size(struct emif_device_details *devices)
541 u32 size_mbytes = 0, temp;
546 if (devices->cs0_device_details) {
547 temp = devices->cs0_device_details->density;
548 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
551 if (devices->cs1_device_details) {
552 temp = devices->cs1_device_details->density;
553 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
555 /* convert to bytes */
556 return size_mbytes << 20;
559 /* Gets the encoding corresponding to a given DMM section size */
560 u32 get_dmm_section_size_map(u32 section_size)
563 * Section size mapping:
564 * 0x0: 16-MiB section
565 * 0x1: 32-MiB section
566 * 0x2: 64-MiB section
567 * 0x3: 128-MiB section
568 * 0x4: 256-MiB section
569 * 0x5: 512-MiB section
573 section_size >>= 24; /* divide by 16 MB */
574 return log_2_n_round_down(section_size);
577 static void emif_calculate_regs(
578 const struct emif_device_details *emif_dev_details,
579 u32 freq, struct emif_regs *regs)
582 const struct lpddr2_addressing *addressing;
583 const struct lpddr2_ac_timings *timings;
584 const struct lpddr2_min_tck *min_tck;
585 const struct lpddr2_device_details *cs0_dev_details =
586 emif_dev_details->cs0_device_details;
587 const struct lpddr2_device_details *cs1_dev_details =
588 emif_dev_details->cs1_device_details;
589 const struct lpddr2_device_timings *cs0_dev_timings =
590 emif_dev_details->cs0_device_timings;
592 emif_assert(emif_dev_details);
595 * You can not have a device on CS1 without one on CS0
596 * So configuring EMIF without a device on CS0 doesn't
599 emif_assert(cs0_dev_details);
600 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
602 * If there is a device on CS1 it should be same type as CS0
603 * (or NVM. But NVM is not supported in this driver yet)
605 emif_assert((cs1_dev_details == NULL) ||
606 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
607 (cs0_dev_details->type == cs1_dev_details->type));
608 emif_assert(freq <= MAX_LPDDR2_FREQ);
610 set_ddr_clk_period(freq);
613 * The device on CS0 is used for all timing calculations
614 * There is only one set of registers for timings per EMIF. So, if the
615 * second CS(CS1) has a device, it should have the same timings as the
618 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
619 emif_assert(timings);
620 min_tck = cs0_dev_timings->min_tck;
622 temp = addressing_table_index(cs0_dev_details->type,
623 cs0_dev_details->density,
624 cs0_dev_details->io_width);
626 emif_assert((temp >= 0));
627 addressing = &(addressing_table[temp]);
628 emif_assert(addressing);
630 sys_freq = get_sys_clk_freq();
632 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
634 addressing, RL_BOOT);
636 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
638 addressing, RL_FINAL);
640 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
642 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
644 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
646 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
648 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
650 regs->temp_alert_config =
651 get_temp_alert_config(cs1_dev_details, addressing, 0);
653 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
654 LPDDR2_VOLTAGE_STABLE);
656 regs->emif_ddr_phy_ctlr_1_init =
657 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
659 regs->emif_ddr_phy_ctlr_1 =
660 get_ddr_phy_ctrl_1(freq, RL_FINAL);
664 print_timing_reg(regs->sdram_config_init);
665 print_timing_reg(regs->sdram_config);
666 print_timing_reg(regs->ref_ctrl);
667 print_timing_reg(regs->sdram_tim1);
668 print_timing_reg(regs->sdram_tim2);
669 print_timing_reg(regs->sdram_tim3);
670 print_timing_reg(regs->read_idle_ctrl);
671 print_timing_reg(regs->temp_alert_config);
672 print_timing_reg(regs->zq_config);
673 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
674 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
676 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
678 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
679 /* Base AC Timing values specified by JESD209-2 for 400MHz operation */
680 static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
681 .max_freq = 400000000,
703 /* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
704 static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
705 .max_freq = 333000000,
727 /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
728 static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
729 .max_freq = 200000000,
752 * Min tCK values specified by JESD209-2
753 * Min tCK specifies the minimum duration of some AC timing parameters in terms
754 * of the number of cycles. If the calculated number of cycles based on the
755 * absolute time value is less than the min tCK value, min tCK value should
756 * be used instead. This typically happens at low frequencies.
758 static const struct lpddr2_min_tck min_tck_jedec = {
773 static const struct lpddr2_ac_timings const*
774 jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
775 &timings_jedec_200_mhz,
776 &timings_jedec_333_mhz,
777 &timings_jedec_400_mhz
780 static const struct lpddr2_device_timings jedec_default_timings = {
781 .ac_timings = jedec_ac_timings,
782 .min_tck = &min_tck_jedec
785 void emif_get_device_timings(u32 emif_nr,
786 const struct lpddr2_device_timings **cs0_device_timings,
787 const struct lpddr2_device_timings **cs1_device_timings)
789 /* Assume Identical devices on EMIF1 & EMIF2 */
790 *cs0_device_timings = &jedec_default_timings;
791 *cs1_device_timings = &jedec_default_timings;
793 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
795 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
796 const char *get_lpddr2_type(u8 type_id)
808 const char *get_lpddr2_io_width(u8 width_id)
811 case LPDDR2_IO_WIDTH_8:
813 case LPDDR2_IO_WIDTH_16:
815 case LPDDR2_IO_WIDTH_32:
822 const char *get_lpddr2_manufacturer(u32 manufacturer)
824 switch (manufacturer) {
825 case LPDDR2_MANUFACTURER_SAMSUNG:
827 case LPDDR2_MANUFACTURER_QIMONDA:
829 case LPDDR2_MANUFACTURER_ELPIDA:
831 case LPDDR2_MANUFACTURER_ETRON:
833 case LPDDR2_MANUFACTURER_NANYA:
835 case LPDDR2_MANUFACTURER_HYNIX:
837 case LPDDR2_MANUFACTURER_MOSEL:
839 case LPDDR2_MANUFACTURER_WINBOND:
841 case LPDDR2_MANUFACTURER_ESMT:
843 case LPDDR2_MANUFACTURER_SPANSION:
845 case LPDDR2_MANUFACTURER_SST:
847 case LPDDR2_MANUFACTURER_ZMOS:
849 case LPDDR2_MANUFACTURER_INTEL:
851 case LPDDR2_MANUFACTURER_NUMONYX:
853 case LPDDR2_MANUFACTURER_MICRON:
860 static void display_sdram_details(u32 emif_nr, u32 cs,
861 struct lpddr2_device_details *device)
864 const char *type_str;
865 char density_str[10];
868 debug("EMIF%d CS%d\t", emif_nr, cs);
875 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
876 type_str = get_lpddr2_type(device->type);
878 density = lpddr2_density_2_size_in_mbytes[device->density];
879 if ((density / 1024 * 1024) == density) {
881 sprintf(density_str, "%d GB", density);
883 sprintf(density_str, "%d MB", density);
884 if (mfg_str && type_str)
885 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
888 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
889 struct lpddr2_device_details *lpddr2_device)
893 mr = get_mr(base, cs, LPDDR2_MR0);
895 /* Mode register value bigger than 8 bit */
899 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
904 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
907 /* DNV supported - But DNV is only supported for NVM */
911 mr = get_mr(base, cs, LPDDR2_MR4);
913 /* Mode register value bigger than 8 bit */
917 mr = get_mr(base, cs, LPDDR2_MR5);
919 /* Mode register value bigger than 8 bit */
923 if (!get_lpddr2_manufacturer(mr)) {
924 /* Manufacturer not identified */
927 lpddr2_device->manufacturer = mr;
929 mr = get_mr(base, cs, LPDDR2_MR6);
931 /* Mode register value bigger than 8 bit */
935 mr = get_mr(base, cs, LPDDR2_MR7);
937 /* Mode register value bigger than 8 bit */
941 mr = get_mr(base, cs, LPDDR2_MR8);
943 /* Mode register value bigger than 8 bit */
947 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
948 if (!get_lpddr2_type(temp)) {
952 lpddr2_device->type = temp;
954 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
955 if (temp > LPDDR2_DENSITY_32Gb) {
956 /* Density not supported */
959 lpddr2_device->density = temp;
961 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
962 if (!get_lpddr2_io_width(temp)) {
963 /* IO width unsupported value */
966 lpddr2_device->io_width = temp;
969 * If all the above tests pass we should
970 * have a device on this chip-select
975 static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
976 struct lpddr2_device_details *lpddr2_dev_details)
979 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
981 if (!lpddr2_dev_details)
984 /* Do the minimum init for mode register accesses */
985 if (!running_from_sdram()) {
986 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
987 writel(phy, &emif->emif_ddr_phy_ctrl_1);
990 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
993 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
995 return lpddr2_dev_details;
998 void emif_get_device_details(u32 emif_nr,
999 struct lpddr2_device_details *cs0_device_details,
1000 struct lpddr2_device_details *cs1_device_details)
1002 u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
1004 if (running_from_sdram()) {
1006 * We can not do automatic discovery running from SDRAM
1007 * Most likely we came here by mistake. Indicate error
1010 cs0_device_details = NULL;
1011 cs1_device_details = NULL;
1014 * Automatically find the device details:
1016 * Reset the PHY after each call to get_lpddr2_details().
1017 * If there is nothing connected to a given chip select
1018 * (typically CS1) mode register reads will mess up with
1019 * the PHY state and subsequent initialization won't work.
1020 * PHY reset brings back PHY to a good state.
1022 cs0_device_details =
1023 get_lpddr2_details(base, CS0, cs0_device_details);
1024 emif_reset_phy(base);
1026 cs1_device_details =
1027 get_lpddr2_details(base, CS1, cs1_device_details);
1028 emif_reset_phy(base);
1031 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1033 static void do_sdram_init(u32 base)
1035 const struct emif_regs *regs;
1036 u32 in_sdram, emif_nr;
1038 debug(">>do_sdram_init() %x\n", base);
1040 in_sdram = running_from_sdram();
1041 emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
1043 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1044 emif_get_reg_dump(emif_nr, ®s);
1046 debug("EMIF: reg dump not provided\n");
1051 * The user has not provided the register values. We need to
1052 * calculate it based on the timings and the DDR frequency
1054 struct emif_device_details dev_details;
1055 struct emif_regs calculated_regs;
1058 * Get device details:
1059 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1060 * - Obtained from user otherwise
1062 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1063 emif_get_device_details(emif_nr, &cs0_dev_details,
1065 dev_details.cs0_device_details = &cs0_dev_details;
1066 dev_details.cs1_device_details = &cs1_dev_details;
1068 /* Return if no devices on this EMIF */
1069 if (!dev_details.cs0_device_details &&
1070 !dev_details.cs1_device_details) {
1071 emif_sizes[emif_nr - 1] = 0;
1076 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
1079 * Get device timings:
1080 * - Default timings specified by JESD209-2 if
1081 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1082 * - Obtained from user otherwise
1084 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1085 &dev_details.cs1_device_timings);
1087 /* Calculate the register values */
1088 emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
1089 regs = &calculated_regs;
1090 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1093 * Initializing the LPDDR2 device can not happen from SDRAM.
1094 * Changing the timing registers in EMIF can happen(going from one
1098 lpddr2_init(base, regs);
1100 /* Write to the shadow registers */
1101 emif_update_timings(base, regs);
1103 debug("<<do_sdram_init() %x\n", base);
1106 void sdram_init_pads(void)
1109 struct control_lpddr2io_regs *lpddr2io_regs =
1110 (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
1111 u32 omap4_rev = omap_revision();
1113 if (omap4_rev == OMAP4430_ES1_0)
1114 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
1115 else if (omap4_rev == OMAP4430_ES2_0)
1116 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
1118 return; /* Post ES2.1 reset values will work */
1120 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
1121 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
1122 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
1123 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
1124 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
1125 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
1127 writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
1130 static void emif_post_init_config(u32 base)
1132 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1133 u32 omap4_rev = omap_revision();
1135 /* reset phy on ES2.0 */
1136 if (omap4_rev == OMAP4430_ES2_0)
1137 emif_reset_phy(base);
1139 /* Put EMIF back in smart idle on ES1.0 */
1140 if (omap4_rev == OMAP4430_ES1_0)
1141 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1144 static void dmm_init(u32 base)
1146 const struct dmm_lisa_map_regs *lisa_map_regs;
1148 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1149 emif_get_dmm_regs(&lisa_map_regs);
1151 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1152 u32 section_cnt, sys_addr;
1153 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1157 sys_addr = CONFIG_SYS_SDRAM_BASE;
1158 emif1_size = emif_sizes[0];
1159 emif2_size = emif_sizes[1];
1160 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1162 if (!emif1_size && !emif2_size)
1165 /* symmetric interleaved section */
1166 if (emif1_size && emif2_size) {
1167 mapped_size = min(emif1_size, emif2_size);
1168 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1169 section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
1171 section_map |= (sys_addr >> 24) <<
1172 OMAP44XX_SYS_ADDR_SHIFT;
1173 section_map |= get_dmm_section_size_map(mapped_size * 2)
1174 << OMAP44XX_SYS_SIZE_SHIFT;
1175 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1176 emif1_size -= mapped_size;
1177 emif2_size -= mapped_size;
1178 sys_addr += (mapped_size * 2);
1183 * Single EMIF section(we can have a maximum of 1 single EMIF
1184 * section- either EMIF1 or EMIF2 or none, but not both)
1187 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1188 section_map |= get_dmm_section_size_map(emif1_size)
1189 << OMAP44XX_SYS_SIZE_SHIFT;
1191 section_map |= (mapped_size >> 24) <<
1192 OMAP44XX_SDRC_ADDR_SHIFT;
1194 section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
1198 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1199 section_map |= get_dmm_section_size_map(emif2_size) <<
1200 OMAP44XX_SYS_SIZE_SHIFT;
1202 section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
1204 section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
1208 if (section_cnt == 2) {
1209 /* Only 1 section - either symmetric or single EMIF */
1210 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1211 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1212 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1214 /* 2 sections - 1 symmetric, 1 single EMIF */
1215 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1216 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1219 /* TRAP for invalid TILER mappings in section 0 */
1220 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1222 lisa_map_regs = &lis_map_regs_calculated;
1224 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1225 (struct dmm_lisa_map_regs *)base;
1227 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1228 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1229 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1230 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1232 writel(lisa_map_regs->dmm_lisa_map_3,
1233 &hw_lisa_map_regs->dmm_lisa_map_3);
1234 writel(lisa_map_regs->dmm_lisa_map_2,
1235 &hw_lisa_map_regs->dmm_lisa_map_2);
1236 writel(lisa_map_regs->dmm_lisa_map_1,
1237 &hw_lisa_map_regs->dmm_lisa_map_1);
1238 writel(lisa_map_regs->dmm_lisa_map_0,
1239 &hw_lisa_map_regs->dmm_lisa_map_0);
1243 * SDRAM initialization:
1244 * SDRAM initialization has two parts:
1245 * 1. Configuring the SDRAM device
1246 * 2. Update the AC timings related parameters in the EMIF module
1247 * (1) should be done only once and should not be done while we are
1248 * running from SDRAM.
1249 * (2) can and should be done more than once if OPP changes.
1250 * Particularly, this may be needed when we boot without SPL and
1251 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1252 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1253 * the frequency. So,
1254 * Doing (1) and (2) makes sense - first time initialization
1255 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1256 * Doing (1) and not (2) doen't make sense
1257 * See do_sdram_init() for the details
1259 void sdram_init(void)
1261 u32 in_sdram, size_prog, size_detect;
1263 debug(">>sdram_init()\n");
1265 if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1268 in_sdram = running_from_sdram();
1269 debug("in_sdram = %d\n", in_sdram);
1273 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1276 do_sdram_init(OMAP44XX_EMIF1);
1277 do_sdram_init(OMAP44XX_EMIF2);
1280 dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
1281 emif_post_init_config(OMAP44XX_EMIF1);
1282 emif_post_init_config(OMAP44XX_EMIF2);
1286 /* for the shadow registers to take effect */
1289 /* Do some testing after the init */
1291 size_prog = omap4_sdram_size();
1292 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1294 /* Compare with the size programmed */
1295 if (size_detect != size_prog) {
1296 printf("SDRAM: identified size not same as expected"
1297 " size identified: %x expected: %x\n",
1301 debug("get_ram_size() successful");
1304 debug("<<sdram_init()\n");