5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/emif.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
35 static inline u32 emif_num(u32 base)
37 if (base == OMAP44XX_EMIF1)
39 else if (base == OMAP44XX_EMIF2)
45 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
48 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
50 mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
51 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
52 if (omap_revision() == OMAP4430_ES2_0)
53 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
55 mr = readl(&emif->emif_lpddr2_mode_reg_data);
56 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
61 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
63 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
65 mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
66 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
67 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
70 void emif_reset_phy(u32 base)
72 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
75 iodft = readl(&emif->emif_iodft_tlgc);
76 iodft |= OMAP44XX_REG_RESET_PHY_MASK;
77 writel(iodft, &emif->emif_iodft_tlgc);
80 static void do_lpddr2_init(u32 base, u32 cs)
84 /* Wait till device auto initialization is complete */
85 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
87 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
90 * Enough loops assuming a maximum of 2GHz
93 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
94 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
96 * Enable refresh along with writing MR2
97 * Encoding of RL in MR2 is (RL - 2)
99 mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
100 set_mr(base, cs, mr_addr, RL_FINAL - 2);
103 static void lpddr2_init(u32 base, const struct emif_regs *regs)
105 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
108 clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
111 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
112 * when EMIF_SDRAM_CONFIG register is written
114 setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
117 * Set the SDRAM_CONFIG and PHY_CTRL for the
118 * un-locked frequency & default RL
120 writel(regs->sdram_config_init, &emif->emif_sdram_config);
121 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
123 do_lpddr2_init(base, CS0);
124 if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
125 do_lpddr2_init(base, CS1);
127 writel(regs->sdram_config, &emif->emif_sdram_config);
128 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
130 /* Enable refresh now */
131 clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
135 static void emif_update_timings(u32 base, const struct emif_regs *regs)
137 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
139 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
140 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
141 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
142 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
143 if (omap_revision() == OMAP4430_ES1_0) {
144 /* ES1 bug EMIF should be in force idle during freq_update */
145 writel(0, &emif->emif_pwr_mgmt_ctrl);
147 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
148 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
150 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
151 writel(regs->zq_config, &emif->emif_zq_config);
152 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
153 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
155 if (omap_revision() >= OMAP4460_ES1_0) {
156 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
157 &emif->emif_l3_config);
159 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
160 &emif->emif_l3_config);
164 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
165 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
167 static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
168 static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
169 static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
172 * Organization and refresh requirements for LPDDR2 devices of different
173 * types and densities. Derived from JESD209-2 section 2.4
175 const struct lpddr2_addressing addressing_table[] = {
176 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
177 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
178 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
179 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
180 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
181 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
182 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
183 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
184 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
185 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
186 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
189 static const u32 lpddr2_density_2_size_in_mbytes[] = {
203 * Calculate the period of DDR clock from frequency value and set the
204 * denominator and numerator in global variables for easy access later
206 static void set_ddr_clk_period(u32 freq)
210 * period_in_ns = 10^9/freq
214 cancel_out(T_num, T_den, 200);
219 * Convert time in nano seconds to number of cycles of DDR clock
221 static inline u32 ns_2_cycles(u32 ns)
223 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
227 * ns_2_cycles with the difference that the time passed is 2 times the actual
228 * value(to avoid fractions). The cycles returned is for the original value of
229 * the timing parameter
231 static inline u32 ns_x2_2_cycles(u32 ns)
233 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
237 * Find addressing table index based on the device's type(S2 or S4) and
240 s8 addressing_table_index(u8 type, u8 density, u8 width)
243 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
247 * Look at the way ADDR_TABLE_INDEX* values have been defined
248 * in emif.h compared to LPDDR2_DENSITY_* values
249 * The table is layed out in the increasing order of density
250 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
253 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
254 index = ADDR_TABLE_INDEX1GS2;
255 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
256 index = ADDR_TABLE_INDEX2GS2;
260 debug("emif: addressing table index %d\n", index);
266 * Find the the right timing table from the array of timing
267 * tables of the device using DDR clock frequency
269 static const struct lpddr2_ac_timings *get_timings_table(const struct
270 lpddr2_ac_timings const *const *device_timings,
273 u32 i, temp, freq_nearest;
274 const struct lpddr2_ac_timings *timings = 0;
276 emif_assert(freq <= MAX_LPDDR2_FREQ);
277 emif_assert(device_timings);
280 * Start with the maximum allowed frequency - that is always safe
282 freq_nearest = MAX_LPDDR2_FREQ;
284 * Find the timings table that has the max frequency value:
285 * i. Above or equal to the DDR frequency - safe
286 * ii. The lowest that satisfies condition (i) - optimal
288 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
289 temp = device_timings[i]->max_freq;
290 if ((temp >= freq) && (temp <= freq_nearest)) {
292 timings = device_timings[i];
295 debug("emif: timings table: %d\n", freq_nearest);
300 * Finds the value of emif_sdram_config_reg
301 * All parameters are programmed based on the device on CS0.
302 * If there is a device on CS1, it will be same as that on CS0 or
303 * it will be NVM. We don't support NVM yet.
304 * If cs1_device pointer is NULL it is assumed that there is no device
307 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
308 const struct lpddr2_device_details *cs1_device,
309 const struct lpddr2_addressing *addressing,
314 config_reg |= (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
315 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
316 OMAP44XX_REG_IBANK_POS_SHIFT;
318 config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
320 config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
322 config_reg |= addressing->row_sz[cs0_device->io_width] <<
323 OMAP44XX_REG_ROWSIZE_SHIFT;
325 config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
327 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
328 OMAP44XX_REG_EBANK_SHIFT;
330 config_reg |= addressing->col_sz[cs0_device->io_width] <<
331 OMAP44XX_REG_PAGESIZE_SHIFT;
336 static u32 get_sdram_ref_ctrl(u32 freq,
337 const struct lpddr2_addressing *addressing)
339 u32 ref_ctrl = 0, val = 0, freq_khz;
340 freq_khz = freq / 1000;
342 * refresh rate to be set is 'tREFI * freq in MHz
343 * division by 10000 to account for khz and x10 in t_REFI_us_x10
345 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
346 ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
351 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
352 const struct lpddr2_min_tck *min_tck,
353 const struct lpddr2_addressing *addressing)
355 u32 tim1 = 0, val = 0;
356 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
357 tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
359 if (addressing->num_banks == BANKS8)
360 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
363 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
365 tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
367 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
368 tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
370 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
371 tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
373 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
374 tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
376 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
377 tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
379 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
380 tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
385 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
386 const struct lpddr2_min_tck *min_tck)
388 u32 tim2 = 0, val = 0;
389 val = max(min_tck->tCKE, timings->tCKE) - 1;
390 tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
392 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
393 tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
396 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
399 val = ns_2_cycles(timings->tXSR) - 1;
400 tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
401 tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
403 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
404 tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
409 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
410 const struct lpddr2_min_tck *min_tck,
411 const struct lpddr2_addressing *addressing)
413 u32 tim3 = 0, val = 0;
414 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
415 tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
417 val = ns_2_cycles(timings->tRFCab) - 1;
418 tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
420 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
421 tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
423 val = ns_2_cycles(timings->tZQCS) - 1;
424 tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
426 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
427 tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
432 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
433 const struct lpddr2_addressing *addressing,
439 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
440 addressing->t_REFI_us_x10;
443 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
444 addressing->t_REFI_us_x10;
445 zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
447 zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
449 zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
451 zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
454 * Assuming that two chipselects have a single calibration resistor
455 * If there are indeed two calibration resistors, then this flag should
456 * be enabled to take advantage of dual calibration feature.
457 * This data should ideally come from board files. But considering
458 * that none of the boards today have calibration resistors per CS,
459 * it would be an unnecessary overhead.
461 zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
463 zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
465 zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
470 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
471 const struct lpddr2_addressing *addressing,
474 u32 alert = 0, interval;
476 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
479 alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
481 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
483 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
485 alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
487 alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
489 alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
494 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
496 u32 idle = 0, val = 0;
498 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
500 /*Maximum value in normal conditions - suggested by hw team */
502 idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
504 idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
509 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
511 u32 phy = 0, val = 0;
513 phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
515 if (freq <= 100000000)
516 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
517 else if (freq <= 200000000)
518 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
520 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
521 phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
523 /* Other fields are constant magic values. Hardcode them together */
524 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
525 OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
530 static u32 get_emif_mem_size(struct emif_device_details *devices)
532 u32 size_mbytes = 0, temp;
537 if (devices->cs0_device_details) {
538 temp = devices->cs0_device_details->density;
539 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
542 if (devices->cs1_device_details) {
543 temp = devices->cs1_device_details->density;
544 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
546 /* convert to bytes */
547 return size_mbytes << 20;
550 /* Gets the encoding corresponding to a given DMM section size */
551 u32 get_dmm_section_size_map(u32 section_size)
554 * Section size mapping:
555 * 0x0: 16-MiB section
556 * 0x1: 32-MiB section
557 * 0x2: 64-MiB section
558 * 0x3: 128-MiB section
559 * 0x4: 256-MiB section
560 * 0x5: 512-MiB section
564 section_size >>= 24; /* divide by 16 MB */
565 return log_2_n_round_down(section_size);
568 static void emif_calculate_regs(
569 const struct emif_device_details *emif_dev_details,
570 u32 freq, struct emif_regs *regs)
573 const struct lpddr2_addressing *addressing;
574 const struct lpddr2_ac_timings *timings;
575 const struct lpddr2_min_tck *min_tck;
576 const struct lpddr2_device_details *cs0_dev_details =
577 emif_dev_details->cs0_device_details;
578 const struct lpddr2_device_details *cs1_dev_details =
579 emif_dev_details->cs1_device_details;
580 const struct lpddr2_device_timings *cs0_dev_timings =
581 emif_dev_details->cs0_device_timings;
583 emif_assert(emif_dev_details);
586 * You can not have a device on CS1 without one on CS0
587 * So configuring EMIF without a device on CS0 doesn't
590 emif_assert(cs0_dev_details);
591 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
593 * If there is a device on CS1 it should be same type as CS0
594 * (or NVM. But NVM is not supported in this driver yet)
596 emif_assert((cs1_dev_details == NULL) ||
597 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
598 (cs0_dev_details->type == cs1_dev_details->type));
599 emif_assert(freq <= MAX_LPDDR2_FREQ);
601 set_ddr_clk_period(freq);
604 * The device on CS0 is used for all timing calculations
605 * There is only one set of registers for timings per EMIF. So, if the
606 * second CS(CS1) has a device, it should have the same timings as the
609 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
610 emif_assert(timings);
611 min_tck = cs0_dev_timings->min_tck;
613 temp = addressing_table_index(cs0_dev_details->type,
614 cs0_dev_details->density,
615 cs0_dev_details->io_width);
617 emif_assert((temp >= 0));
618 addressing = &(addressing_table[temp]);
619 emif_assert(addressing);
621 sys_freq = get_sys_clk_freq();
623 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
625 addressing, RL_BOOT);
627 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
629 addressing, RL_FINAL);
631 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
633 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
635 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
637 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
639 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
641 regs->temp_alert_config =
642 get_temp_alert_config(cs1_dev_details, addressing, 0);
644 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
645 LPDDR2_VOLTAGE_STABLE);
647 regs->emif_ddr_phy_ctlr_1_init =
648 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
650 regs->emif_ddr_phy_ctlr_1 =
651 get_ddr_phy_ctrl_1(freq, RL_FINAL);
655 print_timing_reg(regs->sdram_config_init);
656 print_timing_reg(regs->sdram_config);
657 print_timing_reg(regs->ref_ctrl);
658 print_timing_reg(regs->sdram_tim1);
659 print_timing_reg(regs->sdram_tim2);
660 print_timing_reg(regs->sdram_tim3);
661 print_timing_reg(regs->read_idle_ctrl);
662 print_timing_reg(regs->temp_alert_config);
663 print_timing_reg(regs->zq_config);
664 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
665 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
667 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
669 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
670 /* Base AC Timing values specified by JESD209-2 for 400MHz operation */
671 static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
672 .max_freq = 400000000,
694 /* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
695 static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
696 .max_freq = 333000000,
718 /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
719 static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
720 .max_freq = 200000000,
743 * Min tCK values specified by JESD209-2
744 * Min tCK specifies the minimum duration of some AC timing parameters in terms
745 * of the number of cycles. If the calculated number of cycles based on the
746 * absolute time value is less than the min tCK value, min tCK value should
747 * be used instead. This typically happens at low frequencies.
749 static const struct lpddr2_min_tck min_tck_jedec = {
764 static const struct lpddr2_ac_timings const*
765 jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
766 &timings_jedec_200_mhz,
767 &timings_jedec_333_mhz,
768 &timings_jedec_400_mhz
771 static const struct lpddr2_device_timings jedec_default_timings = {
772 .ac_timings = jedec_ac_timings,
773 .min_tck = &min_tck_jedec
776 void emif_get_device_timings(u32 emif_nr,
777 const struct lpddr2_device_timings **cs0_device_timings,
778 const struct lpddr2_device_timings **cs1_device_timings)
780 /* Assume Identical devices on EMIF1 & EMIF2 */
781 *cs0_device_timings = &jedec_default_timings;
782 *cs1_device_timings = &jedec_default_timings;
784 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
786 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
787 const char *get_lpddr2_type(u8 type_id)
799 const char *get_lpddr2_io_width(u8 width_id)
802 case LPDDR2_IO_WIDTH_8:
804 case LPDDR2_IO_WIDTH_16:
806 case LPDDR2_IO_WIDTH_32:
813 const char *get_lpddr2_manufacturer(u32 manufacturer)
815 switch (manufacturer) {
816 case LPDDR2_MANUFACTURER_SAMSUNG:
818 case LPDDR2_MANUFACTURER_QIMONDA:
820 case LPDDR2_MANUFACTURER_ELPIDA:
822 case LPDDR2_MANUFACTURER_ETRON:
824 case LPDDR2_MANUFACTURER_NANYA:
826 case LPDDR2_MANUFACTURER_HYNIX:
828 case LPDDR2_MANUFACTURER_MOSEL:
830 case LPDDR2_MANUFACTURER_WINBOND:
832 case LPDDR2_MANUFACTURER_ESMT:
834 case LPDDR2_MANUFACTURER_SPANSION:
836 case LPDDR2_MANUFACTURER_SST:
838 case LPDDR2_MANUFACTURER_ZMOS:
840 case LPDDR2_MANUFACTURER_INTEL:
842 case LPDDR2_MANUFACTURER_NUMONYX:
844 case LPDDR2_MANUFACTURER_MICRON:
851 static void display_sdram_details(u32 emif_nr, u32 cs,
852 struct lpddr2_device_details *device)
855 const char *type_str;
856 char density_str[10];
859 debug("EMIF%d CS%d\t", emif_nr, cs);
866 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
867 type_str = get_lpddr2_type(device->type);
869 density = lpddr2_density_2_size_in_mbytes[device->density];
870 if ((density / 1024 * 1024) == density) {
872 sprintf(density_str, "%d GB", density);
874 sprintf(density_str, "%d MB", density);
875 if (mfg_str && type_str)
876 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
879 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
880 struct lpddr2_device_details *lpddr2_device)
884 mr = get_mr(base, cs, LPDDR2_MR0);
886 /* Mode register value bigger than 8 bit */
890 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
895 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
898 /* DNV supported - But DNV is only supported for NVM */
902 mr = get_mr(base, cs, LPDDR2_MR4);
904 /* Mode register value bigger than 8 bit */
908 mr = get_mr(base, cs, LPDDR2_MR5);
910 /* Mode register value bigger than 8 bit */
914 if (!get_lpddr2_manufacturer(mr)) {
915 /* Manufacturer not identified */
918 lpddr2_device->manufacturer = mr;
920 mr = get_mr(base, cs, LPDDR2_MR6);
922 /* Mode register value bigger than 8 bit */
926 mr = get_mr(base, cs, LPDDR2_MR7);
928 /* Mode register value bigger than 8 bit */
932 mr = get_mr(base, cs, LPDDR2_MR8);
934 /* Mode register value bigger than 8 bit */
938 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
939 if (!get_lpddr2_type(temp)) {
943 lpddr2_device->type = temp;
945 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
946 if (temp > LPDDR2_DENSITY_32Gb) {
947 /* Density not supported */
950 lpddr2_device->density = temp;
952 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
953 if (!get_lpddr2_io_width(temp)) {
954 /* IO width unsupported value */
957 lpddr2_device->io_width = temp;
960 * If all the above tests pass we should
961 * have a device on this chip-select
966 static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
967 struct lpddr2_device_details *lpddr2_dev_details)
970 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
972 if (!lpddr2_dev_details)
975 /* Do the minimum init for mode register accesses */
976 if (!running_from_sdram()) {
977 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
978 writel(phy, &emif->emif_ddr_phy_ctrl_1);
981 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
984 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
986 return lpddr2_dev_details;
989 void emif_get_device_details(u32 emif_nr,
990 struct lpddr2_device_details *cs0_device_details,
991 struct lpddr2_device_details *cs1_device_details)
993 u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
995 if (running_from_sdram()) {
997 * We can not do automatic discovery running from SDRAM
998 * Most likely we came here by mistake. Indicate error
1001 cs0_device_details = NULL;
1002 cs1_device_details = NULL;
1005 * Automatically find the device details:
1007 * Reset the PHY after each call to get_lpddr2_details().
1008 * If there is nothing connected to a given chip select
1009 * (typically CS1) mode register reads will mess up with
1010 * the PHY state and subsequent initialization won't work.
1011 * PHY reset brings back PHY to a good state.
1013 cs0_device_details =
1014 get_lpddr2_details(base, CS0, cs0_device_details);
1015 emif_reset_phy(base);
1017 cs1_device_details =
1018 get_lpddr2_details(base, CS1, cs1_device_details);
1019 emif_reset_phy(base);
1022 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1024 static void do_sdram_init(u32 base)
1026 const struct emif_regs *regs;
1027 u32 in_sdram, emif_nr;
1029 debug(">>do_sdram_init() %x\n", base);
1031 in_sdram = running_from_sdram();
1032 emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
1034 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1035 emif_get_reg_dump(emif_nr, ®s);
1037 debug("EMIF: reg dump not provided\n");
1042 * The user has not provided the register values. We need to
1043 * calculate it based on the timings and the DDR frequency
1045 struct emif_device_details dev_details;
1046 struct emif_regs calculated_regs;
1049 * Get device details:
1050 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1051 * - Obtained from user otherwise
1053 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1054 emif_get_device_details(emif_nr, &cs0_dev_details,
1056 dev_details.cs0_device_details = &cs0_dev_details;
1057 dev_details.cs1_device_details = &cs1_dev_details;
1059 /* Return if no devices on this EMIF */
1060 if (!dev_details.cs0_device_details &&
1061 !dev_details.cs1_device_details) {
1062 emif_sizes[emif_nr - 1] = 0;
1067 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
1070 * Get device timings:
1071 * - Default timings specified by JESD209-2 if
1072 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1073 * - Obtained from user otherwise
1075 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1076 &dev_details.cs1_device_timings);
1078 /* Calculate the register values */
1079 emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
1080 regs = &calculated_regs;
1081 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1084 * Initializing the LPDDR2 device can not happen from SDRAM.
1085 * Changing the timing registers in EMIF can happen(going from one
1089 lpddr2_init(base, regs);
1091 /* Write to the shadow registers */
1092 emif_update_timings(base, regs);
1094 debug("<<do_sdram_init() %x\n", base);
1097 void sdram_init_pads(void)
1100 struct control_lpddr2io_regs *lpddr2io_regs =
1101 (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
1102 u32 omap4_rev = omap_revision();
1104 if (omap4_rev == OMAP4430_ES1_0)
1105 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
1106 else if (omap4_rev == OMAP4430_ES2_0)
1107 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
1109 return; /* Post ES2.1 reset values will work */
1111 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
1112 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
1113 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
1114 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
1115 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
1116 writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
1118 writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
1121 static void emif_post_init_config(u32 base)
1123 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1124 u32 omap4_rev = omap_revision();
1126 /* reset phy on ES2.0 */
1127 if (omap4_rev == OMAP4430_ES2_0)
1128 emif_reset_phy(base);
1130 /* Put EMIF back in smart idle on ES1.0 */
1131 if (omap4_rev == OMAP4430_ES1_0)
1132 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1135 static void dmm_init(u32 base)
1137 const struct dmm_lisa_map_regs *lisa_map_regs;
1139 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1140 emif_get_dmm_regs(&lisa_map_regs);
1142 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1143 u32 section_cnt, sys_addr;
1144 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1148 sys_addr = CONFIG_SYS_SDRAM_BASE;
1149 emif1_size = emif_sizes[0];
1150 emif2_size = emif_sizes[1];
1151 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1153 if (!emif1_size && !emif2_size)
1156 /* symmetric interleaved section */
1157 if (emif1_size && emif2_size) {
1158 mapped_size = min(emif1_size, emif2_size);
1159 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1160 section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
1162 section_map |= (sys_addr >> 24) <<
1163 OMAP44XX_SYS_ADDR_SHIFT;
1164 section_map |= get_dmm_section_size_map(mapped_size * 2)
1165 << OMAP44XX_SYS_SIZE_SHIFT;
1166 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1167 emif1_size -= mapped_size;
1168 emif2_size -= mapped_size;
1169 sys_addr += (mapped_size * 2);
1174 * Single EMIF section(we can have a maximum of 1 single EMIF
1175 * section- either EMIF1 or EMIF2 or none, but not both)
1178 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1179 section_map |= get_dmm_section_size_map(emif1_size)
1180 << OMAP44XX_SYS_SIZE_SHIFT;
1182 section_map |= (mapped_size >> 24) <<
1183 OMAP44XX_SDRC_ADDR_SHIFT;
1185 section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
1189 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1190 section_map |= get_dmm_section_size_map(emif2_size) <<
1191 OMAP44XX_SYS_SIZE_SHIFT;
1193 section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
1195 section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
1199 if (section_cnt == 2) {
1200 /* Only 1 section - either symmetric or single EMIF */
1201 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1202 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1203 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1205 /* 2 sections - 1 symmetric, 1 single EMIF */
1206 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1207 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1210 /* TRAP for invalid TILER mappings in section 0 */
1211 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1213 lisa_map_regs = &lis_map_regs_calculated;
1215 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1216 (struct dmm_lisa_map_regs *)base;
1218 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1219 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1220 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1221 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1223 writel(lisa_map_regs->dmm_lisa_map_3,
1224 &hw_lisa_map_regs->dmm_lisa_map_3);
1225 writel(lisa_map_regs->dmm_lisa_map_2,
1226 &hw_lisa_map_regs->dmm_lisa_map_2);
1227 writel(lisa_map_regs->dmm_lisa_map_1,
1228 &hw_lisa_map_regs->dmm_lisa_map_1);
1229 writel(lisa_map_regs->dmm_lisa_map_0,
1230 &hw_lisa_map_regs->dmm_lisa_map_0);
1232 if (omap_revision() >= OMAP4460_ES1_0) {
1234 (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
1236 writel(lisa_map_regs->dmm_lisa_map_3,
1237 &hw_lisa_map_regs->dmm_lisa_map_3);
1238 writel(lisa_map_regs->dmm_lisa_map_2,
1239 &hw_lisa_map_regs->dmm_lisa_map_2);
1240 writel(lisa_map_regs->dmm_lisa_map_1,
1241 &hw_lisa_map_regs->dmm_lisa_map_1);
1242 writel(lisa_map_regs->dmm_lisa_map_0,
1243 &hw_lisa_map_regs->dmm_lisa_map_0);
1248 * SDRAM initialization:
1249 * SDRAM initialization has two parts:
1250 * 1. Configuring the SDRAM device
1251 * 2. Update the AC timings related parameters in the EMIF module
1252 * (1) should be done only once and should not be done while we are
1253 * running from SDRAM.
1254 * (2) can and should be done more than once if OPP changes.
1255 * Particularly, this may be needed when we boot without SPL and
1256 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1257 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1258 * the frequency. So,
1259 * Doing (1) and (2) makes sense - first time initialization
1260 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1261 * Doing (1) and not (2) doen't make sense
1262 * See do_sdram_init() for the details
1264 void sdram_init(void)
1266 u32 in_sdram, size_prog, size_detect;
1268 debug(">>sdram_init()\n");
1270 if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1273 in_sdram = running_from_sdram();
1274 debug("in_sdram = %d\n", in_sdram);
1278 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1281 do_sdram_init(OMAP44XX_EMIF1);
1282 do_sdram_init(OMAP44XX_EMIF2);
1285 dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
1286 emif_post_init_config(OMAP44XX_EMIF1);
1287 emif_post_init_config(OMAP44XX_EMIF2);
1291 /* for the shadow registers to take effect */
1294 /* Do some testing after the init */
1296 size_prog = omap4_sdram_size();
1297 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1299 /* Compare with the size programmed */
1300 if (size_detect != size_prog) {
1301 printf("SDRAM: identified size not same as expected"
1302 " size identified: %x expected: %x\n",
1306 debug("get_ram_size() successful");
1309 debug("<<sdram_init()\n");