3 * HW data initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_common.h>
32 #include <asm/arch/clocks.h>
33 #include <asm/omap_gpio.h>
36 struct prcm_regs const **prcm =
37 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
38 struct dplls const **dplls_data =
39 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
40 struct vcores_data const **omap_vcores =
41 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
42 struct omap_sys_ctrl_regs const **ctrl =
43 (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
46 * The M & N values in the following tables are created using the
48 * tools/omap/clocks_get_m_n.c
49 * Please use this tool for creating the table for any new frequency.
53 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
54 * OMAP4460 OPP_NOM frequency
56 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
57 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
58 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
59 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
60 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
61 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
62 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
63 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
67 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
68 * OMAP4430 OPP_TURBO frequency
70 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
71 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
72 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
73 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
74 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
75 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
76 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
77 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
81 * dpll locked at 1200 MHz - MPU clk at 600 MHz
82 * OMAP4430 OPP_NOM frequency
84 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
85 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
86 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
87 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
88 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
89 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
90 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
91 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
94 /* OMAP4460 OPP_NOM frequency */
95 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
96 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
97 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
98 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
99 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
100 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
101 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
102 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
105 /* OMAP4430 ES1 OPP_NOM frequency */
106 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
107 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
108 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
109 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
110 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
111 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
112 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
113 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
116 /* OMAP4430 ES2.X OPP_NOM frequency */
117 static const struct dpll_params
118 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
119 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
120 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
121 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
122 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
123 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
124 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
125 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
128 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
129 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
130 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
131 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
132 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
133 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
134 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
135 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
138 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
139 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
140 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
141 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
142 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
143 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
144 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
145 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
148 /* ABE M & N values with sys_clk as source */
149 static const struct dpll_params
150 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
151 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
152 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
153 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
154 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
155 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
156 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
157 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
160 /* ABE M & N values with 32K clock as source */
161 static const struct dpll_params abe_dpll_params_32k_196608khz = {
162 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
165 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
166 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
167 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
168 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
169 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
170 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
171 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
172 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
175 struct dplls omap4430_dplls_es1 = {
176 .mpu = mpu_dpll_params_1200mhz,
177 .core = core_dpll_params_es1_1524mhz,
178 .per = per_dpll_params_1536mhz,
179 .iva = iva_dpll_params_1862mhz,
180 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
181 .abe = abe_dpll_params_sysclk_196608khz,
183 .abe = &abe_dpll_params_32k_196608khz,
185 .usb = usb_dpll_params_1920mhz
188 struct dplls omap4430_dplls = {
189 .mpu = mpu_dpll_params_1200mhz,
190 .core = core_dpll_params_1600mhz,
191 .per = per_dpll_params_1536mhz,
192 .iva = iva_dpll_params_1862mhz,
193 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
194 .abe = abe_dpll_params_sysclk_196608khz,
196 .abe = &abe_dpll_params_32k_196608khz,
198 .usb = usb_dpll_params_1920mhz
201 struct dplls omap4460_dplls = {
202 .mpu = mpu_dpll_params_1400mhz,
203 .core = core_dpll_params_1600mhz,
204 .per = per_dpll_params_1536mhz,
205 .iva = iva_dpll_params_1862mhz,
206 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
207 .abe = abe_dpll_params_sysclk_196608khz,
209 .abe = &abe_dpll_params_32k_196608khz,
211 .usb = usb_dpll_params_1920mhz
214 struct pmic_data twl6030_4430es1 = {
215 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
216 .step = 12660, /* 10 mV represented in uV */
217 /* The code starts at 1 not 0 */
221 struct pmic_data twl6030 = {
222 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
223 .step = 12660, /* 10 mV represented in uV */
224 /* The code starts at 1 not 0 */
228 struct pmic_data tps62361 = {
229 .base_offset = TPS62361_BASE_VOLT_MV,
230 .step = 10000, /* 10 mV represented in uV */
232 .gpio = TPS62361_VSEL0_GPIO,
236 struct vcores_data omap4430_volts_es1 = {
238 .mpu.addr = SMPS_REG_ADDR_VCORE1,
239 .mpu.pmic = &twl6030_4430es1,
242 .core.addr = SMPS_REG_ADDR_VCORE3,
243 .core.pmic = &twl6030_4430es1,
246 .mm.addr = SMPS_REG_ADDR_VCORE2,
247 .mm.pmic = &twl6030_4430es1,
250 struct vcores_data omap4430_volts = {
252 .mpu.addr = SMPS_REG_ADDR_VCORE1,
253 .mpu.pmic = &twl6030,
256 .core.addr = SMPS_REG_ADDR_VCORE3,
257 .core.pmic = &twl6030,
260 .mm.addr = SMPS_REG_ADDR_VCORE2,
264 struct vcores_data omap4460_volts = {
266 .mpu.addr = TPS62361_REG_ADDR_SET1,
267 .mpu.pmic = &tps62361,
270 .core.addr = SMPS_REG_ADDR_VCORE1,
271 .core.pmic = &tps62361,
274 .mm.addr = SMPS_REG_ADDR_VCORE2,
275 .mm.pmic = &tps62361,
279 * Enable essential clock domains, modules and
280 * do some additional special settings needed
282 void enable_basic_clocks(void)
284 u32 const clk_domains_essential[] = {
285 (*prcm)->cm_l4per_clkstctrl,
286 (*prcm)->cm_l3init_clkstctrl,
287 (*prcm)->cm_memif_clkstctrl,
288 (*prcm)->cm_l4cfg_clkstctrl,
292 u32 const clk_modules_hw_auto_essential[] = {
293 (*prcm)->cm_l3_gpmc_clkctrl,
294 (*prcm)->cm_memif_emif_1_clkctrl,
295 (*prcm)->cm_memif_emif_2_clkctrl,
296 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
297 (*prcm)->cm_wkup_gpio1_clkctrl,
298 (*prcm)->cm_l4per_gpio2_clkctrl,
299 (*prcm)->cm_l4per_gpio3_clkctrl,
300 (*prcm)->cm_l4per_gpio4_clkctrl,
301 (*prcm)->cm_l4per_gpio5_clkctrl,
302 (*prcm)->cm_l4per_gpio6_clkctrl,
306 u32 const clk_modules_explicit_en_essential[] = {
307 (*prcm)->cm_wkup_gptimer1_clkctrl,
308 (*prcm)->cm_l3init_hsmmc1_clkctrl,
309 (*prcm)->cm_l3init_hsmmc2_clkctrl,
310 (*prcm)->cm_l4per_gptimer2_clkctrl,
311 (*prcm)->cm_wkup_wdtimer2_clkctrl,
312 (*prcm)->cm_l4per_uart3_clkctrl,
316 /* Enable optional additional functional clock for GPIO4 */
317 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
318 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
320 /* Enable 96 MHz clock for MMC1 & MMC2 */
321 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
322 HSMMC_CLKCTRL_CLKSEL_MASK);
323 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
324 HSMMC_CLKCTRL_CLKSEL_MASK);
326 /* Select 32KHz clock as the source of GPTIMER1 */
327 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
328 GPTIMER1_CLKCTRL_CLKSEL_MASK);
330 /* Enable optional 48M functional clock for USB PHY */
331 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
332 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
334 do_enable_clocks(clk_domains_essential,
335 clk_modules_hw_auto_essential,
336 clk_modules_explicit_en_essential,
340 void enable_basic_uboot_clocks(void)
342 u32 const clk_domains_essential[] = {
346 u32 const clk_modules_hw_auto_essential[] = {
347 (*prcm)->cm_l3init_hsusbotg_clkctrl,
348 (*prcm)->cm_l3init_usbphy_clkctrl,
349 (*prcm)->cm_l3init_usbphy_clkctrl,
350 (*prcm)->cm_clksel_usb_60mhz,
351 (*prcm)->cm_l3init_hsusbtll_clkctrl,
355 u32 const clk_modules_explicit_en_essential[] = {
356 (*prcm)->cm_l4per_mcspi1_clkctrl,
357 (*prcm)->cm_l4per_i2c1_clkctrl,
358 (*prcm)->cm_l4per_i2c2_clkctrl,
359 (*prcm)->cm_l4per_i2c3_clkctrl,
360 (*prcm)->cm_l4per_i2c4_clkctrl,
361 (*prcm)->cm_l3init_hsusbhost_clkctrl,
365 do_enable_clocks(clk_domains_essential,
366 clk_modules_hw_auto_essential,
367 clk_modules_explicit_en_essential,
372 * Enable non-essential clock domains, modules and
373 * do some additional special settings needed
375 void enable_non_essential_clocks(void)
377 u32 const clk_domains_non_essential[] = {
378 (*prcm)->cm_mpu_m3_clkstctrl,
379 (*prcm)->cm_ivahd_clkstctrl,
380 (*prcm)->cm_dsp_clkstctrl,
381 (*prcm)->cm_dss_clkstctrl,
382 (*prcm)->cm_sgx_clkstctrl,
383 (*prcm)->cm1_abe_clkstctrl,
384 (*prcm)->cm_c2c_clkstctrl,
385 (*prcm)->cm_cam_clkstctrl,
386 (*prcm)->cm_dss_clkstctrl,
387 (*prcm)->cm_sdma_clkstctrl,
391 u32 const clk_modules_hw_auto_non_essential[] = {
392 (*prcm)->cm_l3instr_l3_3_clkctrl,
393 (*prcm)->cm_l3instr_l3_instr_clkctrl,
394 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
395 (*prcm)->cm_l3init_hsi_clkctrl,
399 u32 const clk_modules_explicit_en_non_essential[] = {
400 (*prcm)->cm1_abe_aess_clkctrl,
401 (*prcm)->cm1_abe_pdm_clkctrl,
402 (*prcm)->cm1_abe_dmic_clkctrl,
403 (*prcm)->cm1_abe_mcasp_clkctrl,
404 (*prcm)->cm1_abe_mcbsp1_clkctrl,
405 (*prcm)->cm1_abe_mcbsp2_clkctrl,
406 (*prcm)->cm1_abe_mcbsp3_clkctrl,
407 (*prcm)->cm1_abe_slimbus_clkctrl,
408 (*prcm)->cm1_abe_timer5_clkctrl,
409 (*prcm)->cm1_abe_timer6_clkctrl,
410 (*prcm)->cm1_abe_timer7_clkctrl,
411 (*prcm)->cm1_abe_timer8_clkctrl,
412 (*prcm)->cm1_abe_wdt3_clkctrl,
413 (*prcm)->cm_l4per_gptimer9_clkctrl,
414 (*prcm)->cm_l4per_gptimer10_clkctrl,
415 (*prcm)->cm_l4per_gptimer11_clkctrl,
416 (*prcm)->cm_l4per_gptimer3_clkctrl,
417 (*prcm)->cm_l4per_gptimer4_clkctrl,
418 (*prcm)->cm_l4per_hdq1w_clkctrl,
419 (*prcm)->cm_l4per_mcbsp4_clkctrl,
420 (*prcm)->cm_l4per_mcspi2_clkctrl,
421 (*prcm)->cm_l4per_mcspi3_clkctrl,
422 (*prcm)->cm_l4per_mcspi4_clkctrl,
423 (*prcm)->cm_l4per_mmcsd3_clkctrl,
424 (*prcm)->cm_l4per_mmcsd4_clkctrl,
425 (*prcm)->cm_l4per_mmcsd5_clkctrl,
426 (*prcm)->cm_l4per_uart1_clkctrl,
427 (*prcm)->cm_l4per_uart2_clkctrl,
428 (*prcm)->cm_l4per_uart4_clkctrl,
429 (*prcm)->cm_wkup_keyboard_clkctrl,
430 (*prcm)->cm_wkup_wdtimer2_clkctrl,
431 (*prcm)->cm_cam_iss_clkctrl,
432 (*prcm)->cm_cam_fdif_clkctrl,
433 (*prcm)->cm_dss_dss_clkctrl,
434 (*prcm)->cm_sgx_sgx_clkctrl,
438 /* Enable optional functional clock for ISS */
439 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
441 /* Enable all optional functional clocks of DSS */
442 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
444 do_enable_clocks(clk_domains_non_essential,
445 clk_modules_hw_auto_non_essential,
446 clk_modules_explicit_en_non_essential,
449 /* Put camera module in no sleep mode */
450 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
451 MODULE_CLKCTRL_MODULEMODE_MASK,
452 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
453 MODULE_CLKCTRL_MODULEMODE_SHIFT);
456 void hw_data_init(void)
458 u32 omap_rev = omap_revision();
460 (*prcm) = &omap4_prcm;
465 *dplls_data = &omap4430_dplls_es1;
466 *omap_vcores = &omap4430_volts_es1;
473 *dplls_data = &omap4430_dplls;
474 *omap_vcores = &omap4430_volts;
479 *dplls_data = &omap4460_dplls;
480 *omap_vcores = &omap4460_volts;
484 printf("\n INVALID OMAP REVISION ");