3 * Common functions for OMAP4 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/armv7.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/sizes.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/omap_common.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
27 static const struct gpio_bank gpio_bank_44xx[6] = {
28 { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
29 { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
30 { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
31 { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
32 { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
33 { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
36 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
38 #ifdef CONFIG_SPL_BUILD
40 * Some tuning of IOs for optimal power and performance
42 void do_io_settings(void)
46 u32 omap4_rev = omap_revision();
48 if (omap4_rev == OMAP4430_ES1_0)
49 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
50 else if (omap4_rev == OMAP4430_ES2_0)
51 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
53 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
56 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
57 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
58 /* No pull for GR10 as per hw team's recommendation */
59 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
60 (*ctrl)->control_lpddr2io1_2);
61 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
64 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
65 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
66 /* No pull for GR10 as per hw team's recommendation */
67 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
68 (*ctrl)->control_lpddr2io2_2);
69 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
72 * Some of these settings (TRIM values) come from eFuse and are
73 * in turn programmed in the eFuse at manufacturing time after
74 * calibration of the device. Do the software over-ride only if
75 * the device is not correctly trimmed
77 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
79 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
80 (*ctrl)->control_ldosram_iva_voltage_ctrl);
82 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
83 (*ctrl)->control_ldosram_mpu_voltage_ctrl);
85 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
86 (*ctrl)->control_ldosram_core_voltage_ctrl);
90 * Over-ride the register
91 * i. unconditionally for all 4430
92 * ii. only if un-trimmed for 4460
94 if (!readl((*ctrl)->control_efuse_1))
95 writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
97 if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
98 writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
100 #endif /* CONFIG_SPL_BUILD */
102 /* dummy fuction for omap4 */
103 void config_data_eye_leveling_samples(u32 emif_base)
107 void init_omap_revision(void)
110 * For some of the ES2/ES1 boards ID_CODE is not reliable:
111 * Also, ES1 and ES2 have different ARM revisions
112 * So use ARM revision for identification
114 unsigned int arm_rev = cortex_rev();
117 case MIDR_CORTEX_A9_R0P1:
118 *omap_si_rev = OMAP4430_ES1_0;
120 case MIDR_CORTEX_A9_R1P2:
121 switch (readl(CONTROL_ID_CODE)) {
122 case OMAP4_CONTROL_ID_CODE_ES2_0:
123 *omap_si_rev = OMAP4430_ES2_0;
125 case OMAP4_CONTROL_ID_CODE_ES2_1:
126 *omap_si_rev = OMAP4430_ES2_1;
128 case OMAP4_CONTROL_ID_CODE_ES2_2:
129 *omap_si_rev = OMAP4430_ES2_2;
132 *omap_si_rev = OMAP4430_ES2_0;
136 case MIDR_CORTEX_A9_R1P3:
137 *omap_si_rev = OMAP4430_ES2_3;
139 case MIDR_CORTEX_A9_R2P10:
140 switch (readl(CONTROL_ID_CODE)) {
141 case OMAP4470_CONTROL_ID_CODE_ES1_0:
142 *omap_si_rev = OMAP4470_ES1_0;
144 case OMAP4460_CONTROL_ID_CODE_ES1_1:
145 *omap_si_rev = OMAP4460_ES1_1;
147 case OMAP4460_CONTROL_ID_CODE_ES1_0:
149 *omap_si_rev = OMAP4460_ES1_0;
154 *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
159 #ifndef CONFIG_SYS_L2CACHE_OFF
160 void v7_outer_cache_enable(void)
162 set_pl310_ctrl_reg(1);
165 void v7_outer_cache_disable(void)
167 set_pl310_ctrl_reg(0);
169 #endif /* !CONFIG_SYS_L2CACHE_OFF */