3 * Common functions for OMAP4 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/armv7.h>
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/sizes.h>
36 #include <asm/arch/gpio.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
42 static const struct gpio_bank gpio_bank_44xx[6] = {
43 { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
44 { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
45 { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
46 { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
47 { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
48 { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
51 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
53 #ifdef CONFIG_SPL_BUILD
55 * Some tuning of IOs for optimal power and performance
57 void do_io_settings(void)
61 u32 omap4_rev = omap_revision();
63 if (omap4_rev == OMAP4430_ES1_0)
64 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
65 else if (omap4_rev == OMAP4430_ES2_0)
66 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
68 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
71 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
72 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
73 /* No pull for GR10 as per hw team's recommendation */
74 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
75 (*ctrl)->control_lpddr2io1_2);
76 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
79 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
80 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
81 /* No pull for GR10 as per hw team's recommendation */
82 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
83 (*ctrl)->control_lpddr2io2_2);
84 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
87 * Some of these settings (TRIM values) come from eFuse and are
88 * in turn programmed in the eFuse at manufacturing time after
89 * calibration of the device. Do the software over-ride only if
90 * the device is not correctly trimmed
92 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
94 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
95 (*ctrl)->control_ldosram_iva_voltage_ctrl);
97 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
98 (*ctrl)->control_ldosram_mpu_voltage_ctrl);
100 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
101 (*ctrl)->control_ldosram_core_voltage_ctrl);
105 * Over-ride the register
106 * i. unconditionally for all 4430
107 * ii. only if un-trimmed for 4460
109 if (!readl((*ctrl)->control_efuse_1))
110 writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
112 if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
113 writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
115 #endif /* CONFIG_SPL_BUILD */
117 /* dummy fuction for omap4 */
118 void config_data_eye_leveling_samples(u32 emif_base)
122 void init_omap_revision(void)
125 * For some of the ES2/ES1 boards ID_CODE is not reliable:
126 * Also, ES1 and ES2 have different ARM revisions
127 * So use ARM revision for identification
129 unsigned int arm_rev = cortex_rev();
132 case MIDR_CORTEX_A9_R0P1:
133 *omap_si_rev = OMAP4430_ES1_0;
135 case MIDR_CORTEX_A9_R1P2:
136 switch (readl(CONTROL_ID_CODE)) {
137 case OMAP4_CONTROL_ID_CODE_ES2_0:
138 *omap_si_rev = OMAP4430_ES2_0;
140 case OMAP4_CONTROL_ID_CODE_ES2_1:
141 *omap_si_rev = OMAP4430_ES2_1;
143 case OMAP4_CONTROL_ID_CODE_ES2_2:
144 *omap_si_rev = OMAP4430_ES2_2;
147 *omap_si_rev = OMAP4430_ES2_0;
151 case MIDR_CORTEX_A9_R1P3:
152 *omap_si_rev = OMAP4430_ES2_3;
154 case MIDR_CORTEX_A9_R2P10:
155 switch (readl(CONTROL_ID_CODE)) {
156 case OMAP4460_CONTROL_ID_CODE_ES1_1:
157 *omap_si_rev = OMAP4460_ES1_1;
159 case OMAP4460_CONTROL_ID_CODE_ES1_0:
161 *omap_si_rev = OMAP4460_ES1_0;
166 *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
171 #ifndef CONFIG_SYS_L2CACHE_OFF
172 void v7_outer_cache_enable(void)
174 set_pl310_ctrl_reg(1);
177 void v7_outer_cache_disable(void)
179 set_pl310_ctrl_reg(0);
181 #endif /* !CONFIG_SYS_L2CACHE_OFF */