git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/omap4/sdram_elpida.c

   1 /*
   2  * Timing and Organization details of the Elpida parts used in OMAP4
   3  * SDPs and Panda
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <asm/emif.h>
  30 #include <asm/arch/sys_proto.h>
  31
  32 /*
  33  * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  34  * SDP and Panda. Since the parts used and geometry are identical for
  35  * SDP and Panda for a given OMAP4 revision, this information is kept
  36  * here instead of being in board directory. However the key functions
  37  * exported are weakly linked so that they can be over-ridden in the board
  38  * directory if there is a OMAP4 board in the future that uses a different
  39  * memory device or geometry.
  40  *
  41  * For any new board with different memory devices over-ride one or more
  42  * of the following functions as per the CONFIG flags you intend to enable:
  43  * - emif_get_reg_dump()
  44  * - emif_get_dmm_regs()
  45  * - emif_get_device_details()
  46  * - emif_get_device_timings()
  47  */
  48
  49 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  50
  51 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  52         .sdram_config_init              = 0x80000eb9,
  53         .sdram_config                   = 0x80001ab9,
  54         .ref_ctrl                       = 0x0000030c,
  55         .sdram_tim1                     = 0x08648311,
  56         .sdram_tim2                     = 0x101b06ca,
  57         .sdram_tim3                     = 0x0048a19f,
  58         .read_idle_ctrl                 = 0x000501ff,
  59         .zq_config                      = 0x500b3214,
  60         .temp_alert_config              = 0xd8016893,
  61         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  62         .emif_ddr_phy_ctlr_1            = 0x049ff808
  63 };
  64
  65 static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  66         .sdram_config_init              = 0x80000eb1,
  67         .sdram_config                   = 0x80001ab1,
  68         .ref_ctrl                       = 0x000005cd,
  69         .sdram_tim1                     = 0x10cb0622,
  70         .sdram_tim2                     = 0x20350d52,
  71         .sdram_tim3                     = 0x00b1431f,
  72         .read_idle_ctrl                 = 0x000501ff,
  73         .zq_config                      = 0x500b3214,
  74         .temp_alert_config              = 0x58016893,
  75         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  76         .emif_ddr_phy_ctlr_1            = 0x049ff418
  77 };
  78
  79 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  80         .sdram_config_init              = 0x80000eb9,
  81         .sdram_config                   = 0x80001ab9,
  82         .ref_ctrl                       = 0x00000618,
  83         .sdram_tim1                     = 0x10eb0662,
  84         .sdram_tim2                     = 0x20370dd2,
  85         .sdram_tim3                     = 0x00b1c33f,
  86         .read_idle_ctrl                 = 0x000501ff,
  87         .zq_config                      = 0xd00b3214,
  88         .temp_alert_config              = 0xd8016893,
  89         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  90         .emif_ddr_phy_ctlr_1            = 0x049ff418
  91 };
  92
  93 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  94         .dmm_lisa_map_0 = 0xFF020100,
  95         .dmm_lisa_map_1 = 0,
  96         .dmm_lisa_map_2 = 0,
  97         .dmm_lisa_map_3 = 0x80540300
  98 };
  99
 100 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 101         .dmm_lisa_map_0 = 0xFF020100,
 102         .dmm_lisa_map_1 = 0,
 103         .dmm_lisa_map_2 = 0,
 104         .dmm_lisa_map_3 = 0x80640300
 105 };
 106
 107 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 108 {
 109         u32 omap4_rev = omap_revision();
 110
 111         /* Same devices and geometry on both EMIFs */
 112         if (omap4_rev == OMAP4430_ES1_0)
 113                 *regs = &emif_regs_elpida_380_mhz_1cs;
 114         else if (omap4_rev == OMAP4430_ES2_0)
 115                 *regs = &emif_regs_elpida_200_mhz_2cs;
 116         else
 117                 *regs = &emif_regs_elpida_400_mhz_2cs;
 118 }
 119 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 120         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 121
 122 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 123                                                 **dmm_lisa_regs)
 124 {
 125         u32 omap_rev = omap_revision();
 126
 127         if (omap_rev == OMAP4430_ES1_0)
 128                 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 129         else
 130                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 131 }
 132
 133 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 134         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 135
 136 #else
 137
 138 static const struct lpddr2_device_details elpida_2G_S4_details = {
 139         .type           = LPDDR2_TYPE_S4,
 140         .density        = LPDDR2_DENSITY_2Gb,
 141         .io_width       = LPDDR2_IO_WIDTH_32,
 142         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 143 };
 144
 145 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 146                         struct lpddr2_device_details *lpddr2_dev_details)
 147 {
 148         u32 omap_rev = omap_revision();
 149
 150         /* EMIF1 & EMIF2 have identical configuration */
 151         if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
 152                 /* Nothing connected on CS1 for ES1.0 */
 153                 return NULL;
 154         } else {
 155                 /* In all other cases Elpida 2G device */
 156                 *lpddr2_dev_details = elpida_2G_S4_details;
 157                 return lpddr2_dev_details;
 158         }
 159 }
 160
 161 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 162                         struct lpddr2_device_details *lpddr2_dev_details)
 163         __attribute__((weak, alias("emif_get_device_details_sdp")));
 164
 165 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 166
 167 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 168 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 169         .max_freq       = 400000000,
 170         .RL             = 6,
 171         .tRPab          = 21,
 172         .tRCD           = 18,
 173         .tWR            = 15,
 174         .tRASmin        = 42,
 175         .tRRD           = 10,
 176         .tWTRx2         = 15,
 177         .tXSR           = 140,
 178         .tXPx2          = 15,
 179         .tRFCab         = 130,
 180         .tRTPx2         = 15,
 181         .tCKE           = 3,
 182         .tCKESR         = 15,
 183         .tZQCS          = 90,
 184         .tZQCL          = 360,
 185         .tZQINIT        = 1000,
 186         .tDQSCKMAXx2    = 11,
 187         .tRASmax        = 70,
 188         .tFAW           = 50
 189 };
 190
 191 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
 192         .max_freq       = 333000000,
 193         .RL             = 5,
 194         .tRPab          = 21,
 195         .tRCD           = 18,
 196         .tWR            = 15,
 197         .tRASmin        = 42,
 198         .tRRD           = 10,
 199         .tWTRx2         = 15,
 200         .tXSR           = 140,
 201         .tXPx2          = 15,
 202         .tRFCab         = 130,
 203         .tRTPx2         = 15,
 204         .tCKE           = 3,
 205         .tCKESR         = 15,
 206         .tZQCS          = 90,
 207         .tZQCL          = 360,
 208         .tZQINIT        = 1000,
 209         .tDQSCKMAXx2    = 11,
 210         .tRASmax        = 70,
 211         .tFAW           = 50
 212 };
 213
 214 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
 215         .max_freq       = 200000000,
 216         .RL             = 3,
 217         .tRPab          = 21,
 218         .tRCD           = 18,
 219         .tWR            = 15,
 220         .tRASmin        = 42,
 221         .tRRD           = 10,
 222         .tWTRx2         = 20,
 223         .tXSR           = 140,
 224         .tXPx2          = 15,
 225         .tRFCab         = 130,
 226         .tRTPx2         = 15,
 227         .tCKE           = 3,
 228         .tCKESR         = 15,
 229         .tZQCS          = 90,
 230         .tZQCL          = 360,
 231         .tZQINIT        = 1000,
 232         .tDQSCKMAXx2    = 11,
 233         .tRASmax        = 70,
 234         .tFAW           = 50
 235 };
 236
 237 static const struct lpddr2_min_tck min_tck_elpida = {
 238         .tRL            = 3,
 239         .tRP_AB         = 3,
 240         .tRCD           = 3,
 241         .tWR            = 3,
 242         .tRAS_MIN       = 3,
 243         .tRRD           = 2,
 244         .tWTR           = 2,
 245         .tXP            = 2,
 246         .tRTP           = 2,
 247         .tCKE           = 3,
 248         .tCKESR         = 3,
 249         .tFAW           = 8
 250 };
 251
 252 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
 253                 &timings_elpida_200_mhz,
 254                 &timings_elpida_333_mhz,
 255                 &timings_elpida_400_mhz
 256 };
 257
 258 static const struct lpddr2_device_timings elpida_2G_S4_timings = {
 259         .ac_timings     = elpida_ac_timings,
 260         .min_tck        = &min_tck_elpida,
 261 };
 262
 263 void emif_get_device_timings_sdp(u32 emif_nr,
 264                 const struct lpddr2_device_timings **cs0_device_timings,
 265                 const struct lpddr2_device_timings **cs1_device_timings)
 266 {
 267         u32 omap_rev = omap_revision();
 268
 269         /* Identical devices on EMIF1 & EMIF2 */
 270         *cs0_device_timings = &elpida_2G_S4_timings;
 271
 272         if (omap_rev == OMAP4430_ES1_0)
 273                 *cs1_device_timings = NULL;
 274         else
 275                 *cs1_device_timings = &elpida_2G_S4_timings;
 276 }
 277
 278 void emif_get_device_timings(u32 emif_nr,
 279                 const struct lpddr2_device_timings **cs0_device_timings,
 280                 const struct lpddr2_device_timings **cs1_device_timings)
 281         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 282
 283 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 284
 285 const struct lpddr2_mr_regs mr_regs = {
 286         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
 287         .mr2    = 0x4,
 288         .mr3    = -1,
 289         .mr10   = MR10_ZQ_ZQINIT,
 290         .mr16   = MR16_REF_FULL_ARRAY
 291 };
 292
 293 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 294 {
 295         *regs = &mr_regs;
 296 }