3 * Clock initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
9 * Sricharan R <r.sricharan@ti.com>
11 * Based on previous work by:
12 * Santosh Shilimkar <santosh.shilimkar@ti.com>
13 * Rajendra Nayak <rnayak@ti.com>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
42 * printing to console doesn't work unless
43 * this code is executed from SPL
45 #define printf(fmt, args...)
49 struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
51 const u32 sys_clk_array[8] = {
52 12000000, /* 12 MHz */
54 16800000, /* 16.8 MHz */
55 19200000, /* 19.2 MHz */
56 26000000, /* 26 MHz */
58 38400000, /* 38.4 MHz */
61 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
62 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
63 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
64 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
65 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
66 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
68 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
71 static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
72 {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
73 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
74 {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
75 {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
76 {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
77 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
78 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
81 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
82 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
83 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
84 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
85 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
86 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
87 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
88 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
91 static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
92 {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
94 {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
95 {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
96 {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
97 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
98 {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
101 static const struct dpll_params
102 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
103 {266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
105 {570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
106 {665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
107 {532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109 {665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
112 static const struct dpll_params
113 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
114 {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
116 {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
117 {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
118 {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
119 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
120 {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
123 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
124 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
125 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
126 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
127 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
128 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
129 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
130 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
133 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
134 {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
135 {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
136 {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
137 {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
138 {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
139 {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
140 {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
143 /* ABE M & N values with sys_clk as source */
144 static const struct dpll_params
145 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
146 {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
147 {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
148 {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
149 {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
150 {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
151 {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
152 {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
155 /* ABE M & N values with 32K clock as source */
156 static const struct dpll_params abe_dpll_params_32k_196608khz = {
157 750, 0, 1, 1, -1, -1, -1, -1
160 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
161 {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
162 {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
163 {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
164 {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
165 {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
166 {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
167 {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
170 void setup_post_dividers(u32 *const base, const struct dpll_params *params)
172 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
174 /* Setup post-dividers */
176 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
178 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
179 if (params->h11 >= 0)
180 writel(params->h11, &dpll_regs->cm_div_h11_dpll);
181 if (params->h12 >= 0)
182 writel(params->h12, &dpll_regs->cm_div_h12_dpll);
183 if (params->h13 >= 0)
184 writel(params->h13, &dpll_regs->cm_div_h13_dpll);
185 if (params->h14 >= 0)
186 writel(params->h14, &dpll_regs->cm_div_h14_dpll);
187 if (params->h22 >= 0)
188 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
189 if (params->h23 >= 0)
190 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
193 const struct dpll_params *get_mpu_dpll_params(void)
195 u32 sysclk_ind = get_sys_clk_index();
196 return &mpu_dpll_params_1100mhz[sysclk_ind];
199 const struct dpll_params *get_core_dpll_params(void)
201 u32 sysclk_ind = get_sys_clk_index();
203 /* Configuring the DDR to be at 532mhz */
204 return &core_dpll_params_2128mhz_ddr266[sysclk_ind];
208 const struct dpll_params *get_per_dpll_params(void)
210 u32 sysclk_ind = get_sys_clk_index();
211 return &per_dpll_params_768mhz[sysclk_ind];
214 const struct dpll_params *get_iva_dpll_params(void)
216 u32 sysclk_ind = get_sys_clk_index();
217 return &iva_dpll_params_2330mhz[sysclk_ind];
220 const struct dpll_params *get_usb_dpll_params(void)
222 u32 sysclk_ind = get_sys_clk_index();
223 return &usb_dpll_params_1920mhz[sysclk_ind];
226 const struct dpll_params *get_abe_dpll_params(void)
228 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
229 u32 sysclk_ind = get_sys_clk_index();
230 return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
232 return &abe_dpll_params_32k_196608khz;
237 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
238 * We set the maximum voltages allowed here because Smart-Reflex is not
239 * enabled in bootloader. Voltage initialization in the kernel will set
240 * these to the nominal values after enabling Smart-Reflex
242 void scale_vcores(void)
248 /* Enable 1.22V from TPS for vdd_mpu */
250 do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
252 /* VCORE 1 - for vdd_core */
254 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
256 /* VCORE 2 - for vdd_MM */
258 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
262 * Enable essential clock domains, modules and
263 * do some additional special settings needed
265 void enable_basic_clocks(void)
267 u32 *const clk_domains_essential[] = {
268 &prcm->cm_l4per_clkstctrl,
269 &prcm->cm_l3init_clkstctrl,
270 &prcm->cm_memif_clkstctrl,
271 &prcm->cm_l4cfg_clkstctrl,
275 u32 *const clk_modules_hw_auto_essential[] = {
276 &prcm->cm_memif_emif_1_clkctrl,
277 &prcm->cm_memif_emif_2_clkctrl,
278 &prcm->cm_l4cfg_l4_cfg_clkctrl,
279 &prcm->cm_wkup_gpio1_clkctrl,
280 &prcm->cm_l4per_gpio2_clkctrl,
281 &prcm->cm_l4per_gpio3_clkctrl,
282 &prcm->cm_l4per_gpio4_clkctrl,
283 &prcm->cm_l4per_gpio5_clkctrl,
284 &prcm->cm_l4per_gpio6_clkctrl,
288 u32 *const clk_modules_explicit_en_essential[] = {
289 &prcm->cm_wkup_gptimer1_clkctrl,
290 &prcm->cm_l3init_hsmmc1_clkctrl,
291 &prcm->cm_l3init_hsmmc2_clkctrl,
292 &prcm->cm_l4per_gptimer2_clkctrl,
293 &prcm->cm_wkup_wdtimer2_clkctrl,
294 &prcm->cm_l4per_uart3_clkctrl,
295 &prcm->cm_l4per_i2c1_clkctrl,
299 /* Enable optional additional functional clock for GPIO4 */
300 setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
301 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
303 /* Enable 96 MHz clock for MMC1 & MMC2 */
304 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
305 HSMMC_CLKCTRL_CLKSEL_MASK);
306 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
307 HSMMC_CLKCTRL_CLKSEL_MASK);
309 /* Select 32KHz clock as the source of GPTIMER1 */
310 setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
311 GPTIMER1_CLKCTRL_CLKSEL_MASK);
313 do_enable_clocks(clk_domains_essential,
314 clk_modules_hw_auto_essential,
315 clk_modules_explicit_en_essential,
319 void enable_basic_uboot_clocks(void)
321 u32 *const clk_domains_essential[] = {
325 u32 *const clk_modules_hw_auto_essential[] = {
329 u32 *const clk_modules_explicit_en_essential[] = {
330 &prcm->cm_l4per_mcspi1_clkctrl,
331 &prcm->cm_l4per_i2c2_clkctrl,
332 &prcm->cm_l4per_i2c3_clkctrl,
333 &prcm->cm_l4per_i2c4_clkctrl,
337 do_enable_clocks(clk_domains_essential,
338 clk_modules_hw_auto_essential,
339 clk_modules_explicit_en_essential,
344 * Enable non-essential clock domains, modules and
345 * do some additional special settings needed
347 void enable_non_essential_clocks(void)
349 u32 *const clk_domains_non_essential[] = {
350 &prcm->cm_mpu_m3_clkstctrl,
351 &prcm->cm_ivahd_clkstctrl,
352 &prcm->cm_dsp_clkstctrl,
353 &prcm->cm_dss_clkstctrl,
354 &prcm->cm_sgx_clkstctrl,
355 &prcm->cm1_abe_clkstctrl,
356 &prcm->cm_c2c_clkstctrl,
357 &prcm->cm_cam_clkstctrl,
358 &prcm->cm_dss_clkstctrl,
359 &prcm->cm_sdma_clkstctrl,
363 u32 *const clk_modules_hw_auto_non_essential[] = {
364 &prcm->cm_mpu_m3_mpu_m3_clkctrl,
365 &prcm->cm_ivahd_ivahd_clkctrl,
366 &prcm->cm_ivahd_sl2_clkctrl,
367 &prcm->cm_dsp_dsp_clkctrl,
368 &prcm->cm_l3_2_gpmc_clkctrl,
369 &prcm->cm_l3instr_l3_3_clkctrl,
370 &prcm->cm_l3instr_l3_instr_clkctrl,
371 &prcm->cm_l3instr_intrconn_wp1_clkctrl,
372 &prcm->cm_l3init_hsi_clkctrl,
373 &prcm->cm_l3init_hsusbtll_clkctrl,
377 u32 *const clk_modules_explicit_en_non_essential[] = {
378 &prcm->cm1_abe_aess_clkctrl,
379 &prcm->cm1_abe_pdm_clkctrl,
380 &prcm->cm1_abe_dmic_clkctrl,
381 &prcm->cm1_abe_mcasp_clkctrl,
382 &prcm->cm1_abe_mcbsp1_clkctrl,
383 &prcm->cm1_abe_mcbsp2_clkctrl,
384 &prcm->cm1_abe_mcbsp3_clkctrl,
385 &prcm->cm1_abe_slimbus_clkctrl,
386 &prcm->cm1_abe_timer5_clkctrl,
387 &prcm->cm1_abe_timer6_clkctrl,
388 &prcm->cm1_abe_timer7_clkctrl,
389 &prcm->cm1_abe_timer8_clkctrl,
390 &prcm->cm1_abe_wdt3_clkctrl,
391 &prcm->cm_l4per_gptimer9_clkctrl,
392 &prcm->cm_l4per_gptimer10_clkctrl,
393 &prcm->cm_l4per_gptimer11_clkctrl,
394 &prcm->cm_l4per_gptimer3_clkctrl,
395 &prcm->cm_l4per_gptimer4_clkctrl,
396 &prcm->cm_l4per_hdq1w_clkctrl,
397 &prcm->cm_l4per_mcspi2_clkctrl,
398 &prcm->cm_l4per_mcspi3_clkctrl,
399 &prcm->cm_l4per_mcspi4_clkctrl,
400 &prcm->cm_l4per_mmcsd3_clkctrl,
401 &prcm->cm_l4per_mmcsd4_clkctrl,
402 &prcm->cm_l4per_mmcsd5_clkctrl,
403 &prcm->cm_l4per_uart1_clkctrl,
404 &prcm->cm_l4per_uart2_clkctrl,
405 &prcm->cm_l4per_uart4_clkctrl,
406 &prcm->cm_wkup_keyboard_clkctrl,
407 &prcm->cm_wkup_wdtimer2_clkctrl,
408 &prcm->cm_cam_iss_clkctrl,
409 &prcm->cm_cam_fdif_clkctrl,
410 &prcm->cm_dss_dss_clkctrl,
411 &prcm->cm_sgx_sgx_clkctrl,
412 &prcm->cm_l3init_hsusbhost_clkctrl,
413 &prcm->cm_l3init_fsusb_clkctrl,
417 /* Enable optional functional clock for ISS */
418 setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
420 /* Enable all optional functional clocks of DSS */
421 setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
423 do_enable_clocks(clk_domains_non_essential,
424 clk_modules_hw_auto_non_essential,
425 clk_modules_explicit_en_non_essential,
428 /* Put camera module in no sleep mode */
429 clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
430 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
431 MODULE_CLKCTRL_MODULEMODE_SHIFT);