3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/omap.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/omap_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/omap_gpio.h>
22 struct prcm_regs const **prcm =
23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
24 struct dplls const **dplls_data =
25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
26 struct vcores_data const **omap_vcores =
27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
28 struct omap_sys_ctrl_regs const **ctrl =
29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
31 /* OPP HIGH FREQUENCY for ES2.0 */
32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
42 /* OPP NOM FREQUENCY for ES1.0 */
43 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
53 /* OPP LOW FREQUENCY for ES1.0 */
54 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
64 /* OPP LOW FREQUENCY for ES2.0 */
65 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
76 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
86 static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
97 static const struct dpll_params
98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
108 static const struct dpll_params
109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
119 static const struct dpll_params
120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
130 static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
141 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
151 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
161 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
163 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
171 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
191 /* ABE M & N values with sys_clk as source */
192 static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
203 /* ABE M & N values with 32K clock as source */
204 static const struct dpll_params abe_dpll_params_32k_196608khz = {
205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
209 static const struct dpll_params
210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
220 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
230 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
250 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
260 struct dplls omap5_dplls_es1 = {
261 .mpu = mpu_dpll_params_800mhz,
262 .core = core_dpll_params_2128mhz_ddr532,
263 .per = per_dpll_params_768mhz,
264 .iva = iva_dpll_params_2330mhz,
265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
266 .abe = abe_dpll_params_sysclk_196608khz,
268 .abe = &abe_dpll_params_32k_196608khz,
270 .usb = usb_dpll_params_1920mhz,
274 struct dplls omap5_dplls_es2 = {
275 .mpu = mpu_dpll_params_1ghz,
276 .core = core_dpll_params_2128mhz_ddr532_es2,
277 .per = per_dpll_params_768mhz_es2,
278 .iva = iva_dpll_params_2330mhz,
279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
280 .abe = abe_dpll_params_sysclk_196608khz,
282 .abe = &abe_dpll_params_32k_196608khz,
284 .usb = usb_dpll_params_1920mhz,
288 struct dplls dra7xx_dplls = {
289 .mpu = mpu_dpll_params_1ghz,
290 .core = core_dpll_params_2128mhz_dra7xx,
291 .per = per_dpll_params_768mhz_dra7xx,
292 .abe = abe_dpll_params_sysclk2_361267khz,
293 .iva = iva_dpll_params_2330mhz_dra7xx,
294 .usb = usb_dpll_params_1920mhz,
295 .ddr = ddr_dpll_params_2128mhz,
296 .gmac = gmac_dpll_params_2000mhz,
299 struct dplls dra72x_dplls = {
300 .mpu = mpu_dpll_params_1ghz,
301 .core = core_dpll_params_2128mhz_dra7xx,
302 .per = per_dpll_params_768mhz_dra7xx,
303 .abe = abe_dpll_params_sysclk2_361267khz,
304 .iva = iva_dpll_params_2330mhz_dra7xx,
305 .usb = usb_dpll_params_1920mhz,
306 .ddr = ddr_dpll_params_2664mhz,
307 .gmac = gmac_dpll_params_2000mhz,
310 struct pmic_data palmas = {
311 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
312 .step = 10000, /* 10 mV represented in uV */
314 * Offset codes 1-6 all give the base voltage in Palmas
315 * Offset code 0 switches OFF the SMPS
318 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
319 .pmic_bus_init = sri2c_init,
320 .pmic_write = omap_vc_bypass_send_value,
323 struct pmic_data tps659038 = {
324 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
325 .step = 10000, /* 10 mV represented in uV */
327 * Offset codes 1-6 all give the base voltage in Palmas
328 * Offset code 0 switches OFF the SMPS
331 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
332 .pmic_bus_init = gpi2c_init,
333 .pmic_write = palmas_i2c_write_u8,
336 struct vcores_data omap5430_volts = {
337 .mpu.value = VDD_MPU,
338 .mpu.addr = SMPS_REG_ADDR_12_MPU,
341 .core.value = VDD_CORE,
342 .core.addr = SMPS_REG_ADDR_8_CORE,
343 .core.pmic = &palmas,
346 .mm.addr = SMPS_REG_ADDR_45_IVA,
350 struct vcores_data omap5430_volts_es2 = {
351 .mpu.value = VDD_MPU_ES2,
352 .mpu.addr = SMPS_REG_ADDR_12_MPU,
355 .core.value = VDD_CORE_ES2,
356 .core.addr = SMPS_REG_ADDR_8_CORE,
357 .core.pmic = &palmas,
359 .mm.value = VDD_MM_ES2,
360 .mm.addr = SMPS_REG_ADDR_45_IVA,
364 struct vcores_data dra752_volts = {
365 .mpu.value = VDD_MPU_DRA752,
366 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
367 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
368 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
369 .mpu.pmic = &tps659038,
371 .eve.value = VDD_EVE_DRA752,
372 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
373 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .eve.addr = TPS659038_REG_ADDR_SMPS45,
375 .eve.pmic = &tps659038,
377 .gpu.value = VDD_GPU_DRA752,
378 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
379 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
380 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
381 .gpu.pmic = &tps659038,
383 .core.value = VDD_CORE_DRA752,
384 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
385 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
386 .core.addr = TPS659038_REG_ADDR_SMPS7,
387 .core.pmic = &tps659038,
389 .iva.value = VDD_IVA_DRA752,
390 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
391 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
392 .iva.addr = TPS659038_REG_ADDR_SMPS8,
393 .iva.pmic = &tps659038,
396 struct vcores_data dra722_volts = {
398 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
399 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
401 .mpu.pmic = &tps659038,
404 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
405 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
407 .eve.pmic = &tps659038,
410 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
411 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
413 .gpu.pmic = &tps659038,
416 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
417 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
419 .core.pmic = &tps659038,
422 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
423 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
425 .iva.pmic = &tps659038,
429 * Enable essential clock domains, modules and
430 * do some additional special settings needed
432 void enable_basic_clocks(void)
434 u32 const clk_domains_essential[] = {
435 (*prcm)->cm_l4per_clkstctrl,
436 (*prcm)->cm_l3init_clkstctrl,
437 (*prcm)->cm_memif_clkstctrl,
438 (*prcm)->cm_l4cfg_clkstctrl,
439 #ifdef CONFIG_DRIVER_TI_CPSW
440 (*prcm)->cm_gmac_clkstctrl,
445 u32 const clk_modules_hw_auto_essential[] = {
446 (*prcm)->cm_l3_gpmc_clkctrl,
447 (*prcm)->cm_memif_emif_1_clkctrl,
448 (*prcm)->cm_memif_emif_2_clkctrl,
449 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
450 (*prcm)->cm_wkup_gpio1_clkctrl,
451 (*prcm)->cm_l4per_gpio2_clkctrl,
452 (*prcm)->cm_l4per_gpio3_clkctrl,
453 (*prcm)->cm_l4per_gpio4_clkctrl,
454 (*prcm)->cm_l4per_gpio5_clkctrl,
455 (*prcm)->cm_l4per_gpio6_clkctrl,
456 (*prcm)->cm_l4per_gpio7_clkctrl,
457 (*prcm)->cm_l4per_gpio8_clkctrl,
461 u32 const clk_modules_explicit_en_essential[] = {
462 (*prcm)->cm_wkup_gptimer1_clkctrl,
463 (*prcm)->cm_l3init_hsmmc1_clkctrl,
464 (*prcm)->cm_l3init_hsmmc2_clkctrl,
465 (*prcm)->cm_l4per_gptimer2_clkctrl,
466 (*prcm)->cm_wkup_wdtimer2_clkctrl,
467 (*prcm)->cm_l4per_uart3_clkctrl,
468 (*prcm)->cm_l4per_i2c1_clkctrl,
469 #ifdef CONFIG_DRIVER_TI_CPSW
470 (*prcm)->cm_gmac_gmac_clkctrl,
473 #ifdef CONFIG_TI_QSPI
474 (*prcm)->cm_l4per_qspi_clkctrl,
479 /* Enable optional additional functional clock for GPIO4 */
480 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
481 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
483 /* Enable 96 MHz clock for MMC1 & MMC2 */
484 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
485 HSMMC_CLKCTRL_CLKSEL_MASK);
486 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
487 HSMMC_CLKCTRL_CLKSEL_MASK);
489 /* Set the correct clock dividers for mmc */
490 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
491 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
492 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
493 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
495 /* Select 32KHz clock as the source of GPTIMER1 */
496 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
497 GPTIMER1_CLKCTRL_CLKSEL_MASK);
499 do_enable_clocks(clk_domains_essential,
500 clk_modules_hw_auto_essential,
501 clk_modules_explicit_en_essential,
504 #ifdef CONFIG_TI_QSPI
505 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
508 /* Enable SCRM OPT clocks for PER and CORE dpll */
509 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
510 OPTFCLKEN_SCRM_PER_MASK);
511 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
512 OPTFCLKEN_SCRM_CORE_MASK);
515 void enable_basic_uboot_clocks(void)
517 u32 const clk_domains_essential[] = {
521 u32 const clk_modules_hw_auto_essential[] = {
522 (*prcm)->cm_l3init_hsusbtll_clkctrl,
526 u32 const clk_modules_explicit_en_essential[] = {
527 (*prcm)->cm_l4per_mcspi1_clkctrl,
528 (*prcm)->cm_l4per_i2c2_clkctrl,
529 (*prcm)->cm_l4per_i2c3_clkctrl,
530 (*prcm)->cm_l4per_i2c4_clkctrl,
531 (*prcm)->cm_l4per_i2c5_clkctrl,
532 (*prcm)->cm_l3init_hsusbhost_clkctrl,
533 (*prcm)->cm_l3init_fsusb_clkctrl,
536 do_enable_clocks(clk_domains_essential,
537 clk_modules_hw_auto_essential,
538 clk_modules_explicit_en_essential,
542 const struct ctrl_ioregs ioregs_omap5430 = {
543 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
544 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
545 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
546 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
547 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
550 const struct ctrl_ioregs ioregs_omap5432_es1 = {
551 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
552 .ctrl_lpddr2ch = 0x0,
553 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
554 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
555 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
556 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
557 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
558 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
561 const struct ctrl_ioregs ioregs_omap5432_es2 = {
562 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
563 .ctrl_lpddr2ch = 0x0,
564 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
565 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
566 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
567 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
568 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
569 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
572 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
573 .ctrl_ddrch = 0x40404040,
574 .ctrl_lpddr2ch = 0x40404040,
575 .ctrl_ddr3ch = 0x80808080,
576 .ctrl_ddrio_0 = 0xA2084210,
577 .ctrl_ddrio_1 = 0x84210840,
578 .ctrl_ddrio_2 = 0x84210000,
579 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
580 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
581 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
584 const struct ctrl_ioregs ioregs_dra72x_es1 = {
585 .ctrl_ddrch = 0x40404040,
586 .ctrl_lpddr2ch = 0x40404040,
587 .ctrl_ddr3ch = 0x60606080,
588 .ctrl_ddrio_0 = 0xA2084210,
589 .ctrl_ddrio_1 = 0x84210840,
590 .ctrl_ddrio_2 = 0x84210000,
591 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
592 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
593 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
596 void __weak hw_data_init(void)
598 u32 omap_rev = omap_revision();
604 *prcm = &omap5_es1_prcm;
605 *dplls_data = &omap5_dplls_es1;
606 *omap_vcores = &omap5430_volts;
612 *prcm = &omap5_es2_prcm;
613 *dplls_data = &omap5_dplls_es2;
614 *omap_vcores = &omap5430_volts_es2;
620 *prcm = &dra7xx_prcm;
621 *dplls_data = &dra7xx_dplls;
622 *omap_vcores = &dra752_volts;
623 *ctrl = &dra7xx_ctrl;
627 *prcm = &dra7xx_prcm;
628 *dplls_data = &dra72x_dplls;
629 *omap_vcores = &dra722_volts;
630 *ctrl = &dra7xx_ctrl;
634 printf("\n INVALID OMAP REVISION ");
638 void get_ioregs(const struct ctrl_ioregs **regs)
640 u32 omap_rev = omap_revision();
645 *regs = &ioregs_omap5430;
648 *regs = &ioregs_omap5432_es1;
651 *regs = &ioregs_omap5432_es2;
655 *regs = &ioregs_dra7xx_es1;
658 *regs = &ioregs_dra72x_es1;
662 printf("\n INVALID OMAP REVISION ");