3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/omap.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/arch/clock.h>
34 #include <asm/omap_gpio.h>
38 struct prcm_regs const **prcm =
39 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
40 struct dplls const **dplls_data =
41 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
42 struct vcores_data const **omap_vcores =
43 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
44 struct omap_sys_ctrl_regs const **ctrl =
45 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
47 /* OPP HIGH FREQUENCY for ES2.0 */
48 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
49 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
50 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
51 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
52 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
53 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
54 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
55 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
58 /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
59 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
60 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
61 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
62 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
63 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
64 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
65 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
66 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
69 /* OPP NOM FREQUENCY for ES1.0 */
70 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
71 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
72 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
73 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
74 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
75 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
76 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
77 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
80 /* OPP LOW FREQUENCY for ES1.0 */
81 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
82 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
83 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
84 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
85 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
86 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
87 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
88 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
91 /* OPP LOW FREQUENCY for ES2.0 */
92 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
93 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
94 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
95 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
96 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
97 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
99 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
102 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
103 {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
105 {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
106 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
107 {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109 {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
110 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
113 static const struct dpll_params
114 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
115 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
116 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
117 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
118 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
119 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
120 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
121 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
124 static const struct dpll_params
125 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
126 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
127 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
128 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
129 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
130 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
131 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
132 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
135 static const struct dpll_params
136 core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
137 {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
138 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
139 {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
140 {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
141 {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
142 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
143 {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
144 {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
147 static const struct dpll_params
148 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
149 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
150 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
151 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
152 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
153 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
154 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
155 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
158 static const struct dpll_params
159 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
160 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
161 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
162 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
163 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
164 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
165 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
166 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
169 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
170 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
171 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
172 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
173 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
174 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
175 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
176 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
179 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
180 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
181 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
182 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
183 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
184 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
185 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
186 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
189 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
190 {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
191 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
192 {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
193 {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
194 {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
196 {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
197 {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
200 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
201 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
202 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
203 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
204 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
205 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
206 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
207 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
210 /* ABE M & N values with sys_clk as source */
211 static const struct dpll_params
212 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
213 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
215 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
216 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
217 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
218 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
219 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
222 /* ABE M & N values with 32K clock as source */
223 static const struct dpll_params abe_dpll_params_32k_196608khz = {
224 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
227 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
228 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
229 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
230 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
231 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
232 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
233 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
234 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
235 {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
238 static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
239 {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
240 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
241 {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
242 {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
243 {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
244 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
245 {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
246 {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
249 struct dplls omap5_dplls_es1 = {
250 .mpu = mpu_dpll_params_800mhz,
251 .core = core_dpll_params_2128mhz_ddr532,
252 .per = per_dpll_params_768mhz,
253 .iva = iva_dpll_params_2330mhz,
254 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
255 .abe = abe_dpll_params_sysclk_196608khz,
257 .abe = &abe_dpll_params_32k_196608khz,
259 .usb = usb_dpll_params_1920mhz,
263 struct dplls omap5_dplls_es2 = {
264 .mpu = mpu_dpll_params_1100mhz,
265 .core = core_dpll_params_2128mhz_ddr532_es2,
266 .per = per_dpll_params_768mhz_es2,
267 .iva = iva_dpll_params_2330mhz,
268 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
269 .abe = abe_dpll_params_sysclk_196608khz,
271 .abe = &abe_dpll_params_32k_196608khz,
273 .usb = usb_dpll_params_1920mhz,
277 struct dplls dra7xx_dplls = {
278 .mpu = mpu_dpll_params_1ghz,
279 .core = core_dpll_params_2128mhz_ddr532_dra7xx,
280 .per = per_dpll_params_768mhz_dra7xx,
281 .usb = usb_dpll_params_1920mhz,
282 .ddr = ddr_dpll_params_1066mhz,
285 struct pmic_data palmas = {
286 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
287 .step = 10000, /* 10 mV represented in uV */
289 * Offset codes 1-6 all give the base voltage in Palmas
290 * Offset code 0 switches OFF the SMPS
293 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
294 .pmic_bus_init = sri2c_init,
295 .pmic_write = omap_vc_bypass_send_value,
298 struct pmic_data tps659038 = {
299 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
300 .step = 10000, /* 10 mV represented in uV */
302 * Offset codes 1-6 all give the base voltage in Palmas
303 * Offset code 0 switches OFF the SMPS
306 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
307 .pmic_bus_init = gpi2c_init,
308 .pmic_write = palmas_i2c_write_u8,
311 struct vcores_data omap5430_volts = {
312 .mpu.value = VDD_MPU,
313 .mpu.addr = SMPS_REG_ADDR_12_MPU,
316 .core.value = VDD_CORE,
317 .core.addr = SMPS_REG_ADDR_8_CORE,
318 .core.pmic = &palmas,
321 .mm.addr = SMPS_REG_ADDR_45_IVA,
325 struct vcores_data omap5430_volts_es2 = {
326 .mpu.value = VDD_MPU_ES2,
327 .mpu.addr = SMPS_REG_ADDR_12_MPU,
330 .core.value = VDD_CORE_ES2,
331 .core.addr = SMPS_REG_ADDR_8_CORE,
332 .core.pmic = &palmas,
334 .mm.value = VDD_MM_ES2,
335 .mm.addr = SMPS_REG_ADDR_45_IVA,
339 struct vcores_data dra752_volts = {
340 .mpu.value = VDD_MPU_DRA752,
341 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
342 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
343 .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
344 .mpu.pmic = &tps659038,
346 .eve.value = VDD_EVE_DRA752,
347 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
348 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
349 .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
350 .eve.pmic = &tps659038,
352 .gpu.value = VDD_GPU_DRA752,
353 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
354 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
356 .gpu.pmic = &tps659038,
358 .core.value = VDD_CORE_DRA752,
359 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
360 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
361 .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
362 .core.pmic = &tps659038,
364 .iva.value = VDD_IVA_DRA752,
365 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
366 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
367 .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
368 .iva.pmic = &tps659038,
372 * Enable essential clock domains, modules and
373 * do some additional special settings needed
375 void enable_basic_clocks(void)
377 u32 const clk_domains_essential[] = {
378 (*prcm)->cm_l4per_clkstctrl,
379 (*prcm)->cm_l3init_clkstctrl,
380 (*prcm)->cm_memif_clkstctrl,
381 (*prcm)->cm_l4cfg_clkstctrl,
385 u32 const clk_modules_hw_auto_essential[] = {
386 (*prcm)->cm_l3_gpmc_clkctrl,
387 (*prcm)->cm_memif_emif_1_clkctrl,
388 (*prcm)->cm_memif_emif_2_clkctrl,
389 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
390 (*prcm)->cm_wkup_gpio1_clkctrl,
391 (*prcm)->cm_l4per_gpio2_clkctrl,
392 (*prcm)->cm_l4per_gpio3_clkctrl,
393 (*prcm)->cm_l4per_gpio4_clkctrl,
394 (*prcm)->cm_l4per_gpio5_clkctrl,
395 (*prcm)->cm_l4per_gpio6_clkctrl,
399 u32 const clk_modules_explicit_en_essential[] = {
400 (*prcm)->cm_wkup_gptimer1_clkctrl,
401 (*prcm)->cm_l3init_hsmmc1_clkctrl,
402 (*prcm)->cm_l3init_hsmmc2_clkctrl,
403 (*prcm)->cm_l4per_gptimer2_clkctrl,
404 (*prcm)->cm_wkup_wdtimer2_clkctrl,
405 (*prcm)->cm_l4per_uart3_clkctrl,
406 (*prcm)->cm_l4per_i2c1_clkctrl,
410 /* Enable optional additional functional clock for GPIO4 */
411 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
412 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
414 /* Enable 96 MHz clock for MMC1 & MMC2 */
415 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
416 HSMMC_CLKCTRL_CLKSEL_MASK);
417 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
418 HSMMC_CLKCTRL_CLKSEL_MASK);
420 /* Set the correct clock dividers for mmc */
421 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
422 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
423 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
424 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
426 /* Select 32KHz clock as the source of GPTIMER1 */
427 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
428 GPTIMER1_CLKCTRL_CLKSEL_MASK);
430 do_enable_clocks(clk_domains_essential,
431 clk_modules_hw_auto_essential,
432 clk_modules_explicit_en_essential,
435 /* Enable SCRM OPT clocks for PER and CORE dpll */
436 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
437 OPTFCLKEN_SCRM_PER_MASK);
438 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
439 OPTFCLKEN_SCRM_CORE_MASK);
442 void enable_basic_uboot_clocks(void)
444 u32 const clk_domains_essential[] = {
448 u32 const clk_modules_hw_auto_essential[] = {
449 (*prcm)->cm_l3init_hsusbtll_clkctrl,
453 u32 const clk_modules_explicit_en_essential[] = {
454 (*prcm)->cm_l4per_mcspi1_clkctrl,
455 (*prcm)->cm_l4per_i2c2_clkctrl,
456 (*prcm)->cm_l4per_i2c3_clkctrl,
457 (*prcm)->cm_l4per_i2c4_clkctrl,
458 (*prcm)->cm_l4per_i2c5_clkctrl,
459 (*prcm)->cm_l3init_hsusbhost_clkctrl,
460 (*prcm)->cm_l3init_fsusb_clkctrl,
464 do_enable_clocks(clk_domains_essential,
465 clk_modules_hw_auto_essential,
466 clk_modules_explicit_en_essential,
471 * Enable non-essential clock domains, modules and
472 * do some additional special settings needed
474 void enable_non_essential_clocks(void)
476 u32 const clk_domains_non_essential[] = {
477 (*prcm)->cm_mpu_m3_clkstctrl,
478 (*prcm)->cm_ivahd_clkstctrl,
479 (*prcm)->cm_dsp_clkstctrl,
480 (*prcm)->cm_dss_clkstctrl,
481 (*prcm)->cm_sgx_clkstctrl,
482 (*prcm)->cm1_abe_clkstctrl,
483 (*prcm)->cm_c2c_clkstctrl,
484 (*prcm)->cm_cam_clkstctrl,
485 (*prcm)->cm_dss_clkstctrl,
486 (*prcm)->cm_sdma_clkstctrl,
490 u32 const clk_modules_hw_auto_non_essential[] = {
491 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
492 (*prcm)->cm_ivahd_ivahd_clkctrl,
493 (*prcm)->cm_ivahd_sl2_clkctrl,
494 (*prcm)->cm_dsp_dsp_clkctrl,
495 (*prcm)->cm_l3instr_l3_3_clkctrl,
496 (*prcm)->cm_l3instr_l3_instr_clkctrl,
497 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
498 (*prcm)->cm_l3init_hsi_clkctrl,
499 (*prcm)->cm_l4per_hdq1w_clkctrl,
503 u32 const clk_modules_explicit_en_non_essential[] = {
504 (*prcm)->cm1_abe_aess_clkctrl,
505 (*prcm)->cm1_abe_pdm_clkctrl,
506 (*prcm)->cm1_abe_dmic_clkctrl,
507 (*prcm)->cm1_abe_mcasp_clkctrl,
508 (*prcm)->cm1_abe_mcbsp1_clkctrl,
509 (*prcm)->cm1_abe_mcbsp2_clkctrl,
510 (*prcm)->cm1_abe_mcbsp3_clkctrl,
511 (*prcm)->cm1_abe_slimbus_clkctrl,
512 (*prcm)->cm1_abe_timer5_clkctrl,
513 (*prcm)->cm1_abe_timer6_clkctrl,
514 (*prcm)->cm1_abe_timer7_clkctrl,
515 (*prcm)->cm1_abe_timer8_clkctrl,
516 (*prcm)->cm1_abe_wdt3_clkctrl,
517 (*prcm)->cm_l4per_gptimer9_clkctrl,
518 (*prcm)->cm_l4per_gptimer10_clkctrl,
519 (*prcm)->cm_l4per_gptimer11_clkctrl,
520 (*prcm)->cm_l4per_gptimer3_clkctrl,
521 (*prcm)->cm_l4per_gptimer4_clkctrl,
522 (*prcm)->cm_l4per_mcspi2_clkctrl,
523 (*prcm)->cm_l4per_mcspi3_clkctrl,
524 (*prcm)->cm_l4per_mcspi4_clkctrl,
525 (*prcm)->cm_l4per_mmcsd3_clkctrl,
526 (*prcm)->cm_l4per_mmcsd4_clkctrl,
527 (*prcm)->cm_l4per_mmcsd5_clkctrl,
528 (*prcm)->cm_l4per_uart1_clkctrl,
529 (*prcm)->cm_l4per_uart2_clkctrl,
530 (*prcm)->cm_l4per_uart4_clkctrl,
531 (*prcm)->cm_wkup_keyboard_clkctrl,
532 (*prcm)->cm_wkup_wdtimer2_clkctrl,
533 (*prcm)->cm_cam_iss_clkctrl,
534 (*prcm)->cm_cam_fdif_clkctrl,
535 (*prcm)->cm_dss_dss_clkctrl,
536 (*prcm)->cm_sgx_sgx_clkctrl,
540 /* Enable optional functional clock for ISS */
541 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
543 /* Enable all optional functional clocks of DSS */
544 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
546 do_enable_clocks(clk_domains_non_essential,
547 clk_modules_hw_auto_non_essential,
548 clk_modules_explicit_en_non_essential,
551 /* Put camera module in no sleep mode */
552 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
553 MODULE_CLKCTRL_MODULEMODE_MASK,
554 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
555 MODULE_CLKCTRL_MODULEMODE_SHIFT);
558 const struct ctrl_ioregs ioregs_omap5430 = {
559 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
560 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
561 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
562 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
563 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
566 const struct ctrl_ioregs ioregs_omap5432_es1 = {
567 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
568 .ctrl_lpddr2ch = 0x0,
569 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
570 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
571 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
572 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
573 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
576 const struct ctrl_ioregs ioregs_omap5432_es2 = {
577 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
578 .ctrl_lpddr2ch = 0x0,
579 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
580 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
581 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
582 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
583 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
586 void hw_data_init(void)
588 u32 omap_rev = omap_revision();
594 *prcm = &omap5_es1_prcm;
595 *dplls_data = &omap5_dplls_es1;
596 *omap_vcores = &omap5430_volts;
602 *prcm = &omap5_es2_prcm;
603 *dplls_data = &omap5_dplls_es2;
604 *omap_vcores = &omap5430_volts_es2;
609 *prcm = &dra7xx_prcm;
610 *dplls_data = &dra7xx_dplls;
611 *omap_vcores = &dra752_volts;
612 *ctrl = &dra7xx_ctrl;
616 printf("\n INVALID OMAP REVISION ");
620 void get_ioregs(const struct ctrl_ioregs **regs)
622 u32 omap_rev = omap_revision();
627 *regs = &ioregs_omap5430;
630 *regs = &ioregs_omap5432_es1;
634 *regs = &ioregs_omap5432_es2;
638 printf("\n INVALID OMAP REVISION ");